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When a module is not used for certine amount of time......
then its IO values are not changed........
at this time the clk is still operation...this is loss of power.......
so use a gate to diable(we need to disable only edges not the whole clk)clk......
no togglings in clk......no changes in the moules state....then the power is saved..........
u may ask......it better to disable the vdd when the module is not used.....
but in gating....we r saving power logically........if ur going for vdd...u cant use logic....
how to make a clk gate????
many solutions.......one aim......remove the edge.....
use or gate with 1 as controle signal............
use and gate 0 as control signal......
now think and come up with some ideas and give me some solutions for gating a clk....
Clock gating is now a pretty easy technique in Power Compiler and Clock gaters are inserted automatically.
In fact you may even save some area as some multiplexers can be integrated in the gating circuitry.
Isolating VDD and making independent power island is a lot more complex and even required level holders and other nasty stuff....
Re: Gated Clock.............What is this....and its Advantag
Clock gating is a power reduction technique thats used in modern day ASIC designs. Here depending on the architecture, clocks are gated to parts of the design, if we are aware that those parts are not going to be functional. This helps in power reduction because it reduces the switching power component in the total power.
Re: Gated Clock.............What is this....and its Advantag
gated clock is clock input to a system through a gate. for example for a two input "and gate" if one input is clock and another input is 1 then the clock will appear at output as it is.( for time being forget about gate delay) But if I make other input of "and gate "which was initially 1 to 0, then the output becomes 0,thus there is no clock .
It is basically used for 1] power saving 2] system standby
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