alpeshchokshi
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Hi Friends,
Can any body help me with the designing of FSM of below problem???
Design a logic which mimics a infinite width register. It takes input serially 1 bit at a time. Output is asserted high when this register holds a value which is divisible by 5.
Input Sequence Value Output
1 1 1 0
0 10 2 0
1 101 5 1
0 1010 10 1
1 10101 21 0
Thanking you in advance
Regards,
Can any body help me with the designing of FSM of below problem???
Design a logic which mimics a infinite width register. It takes input serially 1 bit at a time. Output is asserted high when this register holds a value which is divisible by 5.
Input Sequence Value Output
1 1 1 0
0 10 2 0
1 101 5 1
0 1010 10 1
1 10101 21 0
Thanking you in advance
Regards,
