How to deside the value of the Compensate Capacitance?

How to deside the value of the Compensate Capacitance, i.e. CC when design a OPA? In the book "CMOS Analog Circuit Design" writed by Allen, I found because of the second pole p2=gmII/CL, the zero z=gmII/CC, and the GBW is gmI/CC, so we can know that CL=2.2CC, where the CL is the Load Capacitance.

But in most condiction, the CC not only depends on the Load Capacitance, i.e. CL, but also depends on the Parasite Capacitance, i.e. C01, for example the formula in the attachment, we can find that CC is deside by the CL and C01.

My question is: when we start to design OPA, we do no know the value of w/l, so we do not know the value of C01 either! So, for example, from the formula in the attachment, how to deside the value of the Compensate Capacitance, i.e. CC when start to design a OPA?

Help me please, thanx!!!

The formula can be found in the paper "A Compensation Strategy for Two-Stage
CMOS Opamps Based on Current Buffer" writed by G. Palmisano and G. Palumbo.

normally 20% of the load cap for rule of thrump

yaxazaa said:

normally 20% of the load cap for rule of thrump

Click to expand...

why? can you give some illustrations.
thanks

Hi yaxazaa: can you explain it detailed? thanx!

I think you have to consider the GBW, capacitor size and phase margin(with compensate resistor) together. Formula calculation can only provide a round value.

You should not try to come with an exact value for the Cc before you even start the design. Better, try to find a starting value which you later can optimize when you have at least one itteration of the design. A good starting point is GBW=gm1/Cc. You should know the GBW as a spec to your design. You can estimate gm1 if you know how much current you can afford for the first stage. Start from here. The important point is to start the design afterall, isn't it?
Sometimes, Cc is completely defined by noise considerations from something like kT/Cc

I add that the compensation capacitor Cc controls both the slew rate and the open-loop bandwidth where e.g. SR = Iss/Cc amd BW = gm2/Cc.

The SR is supposed to be given as a spec. Also the open-loop bandwidth can be got from the specs of open-loop gain and the unity-gain frequency as Wu = Ao*BW.

I hope I helped you!

I noly used two-stage opamp in pipeline ADC.
In our design, we chose Cc according SNR, i.e. Cc is chosen according to noise spec, large Cc -> low noise, also big power consumption.
we try to choose the smallest value of Cc to minimize power.

BR
wdd