how we can test the settling time of fully differential ampl

hi
as mentioned up, i have fully op amp 1.2v, i want see the settling time could some one help me to that
regards

Re: how we can test the settling time of fully differential

Hi wael_wael
As you know, the settling time of any system is defind as the time it takes to reach its final value with a specified error (ess) after giving a step signal to the input. For an opamp there are two types of settling: small-signal settling and large-signal settling (aka "slewing"). If the input is small enough, only small-signal (linear) settling would occur. Otherwise, first the output slews and after it reaches enough the final value, te output will show small-signal settling behavior until it reaches the required error. Hence the total settling time (ts) is consisted of large-signal settling time (tls) and small-signal settling time (tss).
For testing of settling time, you should first use the example opamp in a closed-loop form, e.g., in a unity-gain buffer structure. Then the input should be excited by a step signal (in simulators such as HSPICE usually a pulse signal with large period is used) and the output signal is probed (measured). On can plot the output after simultion (for example by avanwaves in the case of HSPICE simulation) to measure exactly the settling time. Ofcourse in a fully-differential opamp, the input should be differential as well as the output (while writing the netlist, one can access the differential output using Exxx (voltage controlled voltae source (vcvs)) component. A somehow similar conversion should be applied to the input using vcvs blocks).

In the above figure, main concepts of settling time (as mentioned earlier) are shown.

Regards,
EZT