What is Clock Reconvergence?

reconvergence

what is "clock reconvergence" ?

clock reconvergence

when you a multi clock domain ckt, and when two clocks reach the same logic endpoint from different paths ...you have a reconvergence problem..you need to either delay one clock or use some clock domain syncronization techniques to avoid this...

reconvergence

Find attached document on this topic.

best regards,
subbu.

what is clock reconvergence

research.sun.com/async2003/Talks/Async_TWilliams_14may03.pdf

clock convergence

kbulusu said:

when you a multi clock domain ckt, and when two clocks reach the same logic endpoint from different paths ...you have a reconvergence problem..you need to either delay one clock or use some clock domain syncronization techniques to avoid this...

Click to expand...

My thinking it is a single clock domain. If two clocks seem to converge than it is more or less a overlapping clocks problem and does not fall into clock convergence.

Srinath

reconverging

shahal said:

what is "clock reconvergence" ?

Click to expand...

Depends on the context...

In static-timing-analysis, clock-reconvergence describes the situation where you perform multi-corner (best-case, worst-case) analysis. For a timing-path in your design, there are two important flops: driving-flop and capture-flop. If these two share part of the clock-tree, then 'reconvergence' refers to the timing-analyzer's treatment of the clock-tree delay.

pessimistic reconvergence means the analyzer will always pick the 'worst-case' timing independently for drivingflop and capture-flop.

optimisitc reconvergence means the analyzer will use the same offset for the part of the clock-tree common to both flops. This is more realistic, since in the physical sense, one part of the clock-tree cannot run at worst-case and best-case corner simultaneously.

In clock-tree synthesis (CTS), reconvergence is when any node in your clock-tree has more than one input (fan-in) from itself. For example, a lot of designs have bypassable-PLL circuits. If the bypass-mux is in the RTL, then the CTS-tool thinks the primary-port branches out to two distinct branches, which then 'collapse' back into itself. (If the bypass-mux is in the PLL macro, then the tree still reconverges, but it is hidden from the CTS-tool.)

Reconvergence is not necessarily a bad thing -- it just makes ASIC-engineer's life more complicated.

clock reconvergence

good document

clock convergence

This is a good paper which explains the term and also CDC


(Paper on clk domain crossing from Cadence)
HTH,
B

clock domain crossing + reconvergence

i like modelsim62c's answer
there are two interpretations. i wish there was more detail in the first one though, because the second one seems to be more popular.

explain overlapping clock domains

3x for the document

reconvergence clock

cadence white paper could be a better solution

Can someone please help to understand how Clock re-convergence cause Non-unateness ?

hi,

You can find few important information in the following path also. In one of the thread I was mention but I forget that .. so pasting the link once again.

Clock Reconvergence Pessimism (CRP) basic |VLSI Concepts

any ebooks related to this can share.