Request for Advanced STA Interview Questions

sta interview questions

Hello, can some one please share with me some specific questions for an STA Interview? Something on the advanced level please, not something like "what is setup and hold," or how do you use "virtual clocks" etc. I really appreciate your help. It also could be some problems you ran into during STA, etc.. Ofcourse solutions along with the problems would be greatly appreciated.

sta interview questions

Seriously guys.. no takers? Would really appareciate any help I can get on this.

sta interview question

Hi Shahal................

well in the Recent interviews i attended the questions were basically belonging to
1)Glitches and Hazards
2)Clock Skew
3)Double Synchronizers
4)FIFO design
5)Latch Based Designs

I couldn't perform well but i came to know abt these things recently and also i uploaded the material relating to the above topics recently as free mirrors(no points required)on 26 and 28 JAN 2007 in this subforum

good luck

interview questions for sta

Rakesh... Do you remember any of the questions..anything at all?

logic design sta questions

shahal,
advanced STA questions will be more related to OCV (on chip variation ) , CPP ( common path pessimisim), how to calculate it...they will most likely draw a clk tree and a datapath , they will give you some values and will ask you to account for CPP and will ask you whether the given ckt meets timing or not ...

there will be questions on Crosstalk/SI and how they effect the timing,
there will be questions on calculation of clk latencies, insertion delays etc and methods to fix it..

some ppl will give draw logic diagram and give some values like network delay, IO delay , clk freq, etc and will ask you write the Magma / synopsys design constraints for the ckt...they might ask you questions on multi-cycle paths , false paths ; some ppl might ask you on how you can identify a false path given a ckt..they are looking for your approach and not for correct answer since for a given design there can be thousands of timing constraints.

Questions on multi-corner and multi-mode also might popup occasinally...
Other questions might involve disabling timing arcs and calculate the slack for a given path....some theoritical questions can involve explanation of setup and hold times, input/output delays, if it is an EDA industry, then some techniques on identifying and generating timing exceptions automatically..why are timing exceptions dangerous and when are they useful? Some questions on back annotation etc it really depends on the company and the position like its frontend or backend or whether it is overall timing closure...

Whatever rakesh pointed out are also good..but u see them normally for clock domain crossing analysis and are really important for a functional verification purposes...I I personally feel STA wise,,it doesnt matter

I hope this helps..

Added after 4 minutes:

just make sure u study the small but imp topics like slew calculation and how and when and why do you impose the slew limits...also questions like how slew and fanout limits affect timing ..how and when do you want to derate timing etc...

interview questions sta

Hi Shahal...these are some of the questions.....

1)Calculate Depth of FIFO
2)Two ckts present one is at High Speed and other at Low Speed ....How to synchronize these two
3)Metastability Concepts
4)What is Latency..Adv and Disadv of Latency
5)Pipelining....Adv and Disadv of Pipelining
6)Latch Based Design and Issues
7)PLL and DLL concepts
8)What to do If Hold Time Violation Occurs

advanced sta

Well my interview s**ked.

So what is "source synchronous?"
We care about OCV for both setup and hold or only setup?
Do we care about clock uncertainity for hold in synthesis?

oh well..

magma interview

shahal,
sorry to know that it didnt go well..I'm not sure what ur experience is and in which domain..but those were not so hard questions..anyways good luck with ur interviews