ywguo
Junior Member level 2
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compile_seqmap_propagate_constants
Hi, Guys,
RTL vs. netlist verification failed using formality. I checked the report and netlist, RTL code. Some registers and logics gates are reduced because the register was always '0' or '1'. The reduction didn't affect the function.
How do I write the script to make Formality give a correct answer?
Thanks
Yawei
Hi, Guys,
RTL vs. netlist verification failed using formality. I checked the report and netlist, RTL code. Some registers and logics gates are reduced because the register was always '0' or '1'. The reduction didn't affect the function.
How do I write the script to make Formality give a correct answer?
Thanks
Yawei