OTA design .... urgent help needed

The project aims at the design of a fully-differential OTA to be used as a unity-gain buffer
in switched-capacitor filter applications. The expected load is 1 pF on each side as
shown below. The amplifier is required to accommodate a maximum swing of 3 V differential-
peak-to-peak running at 40 MHz and applied to the input of the amplifier. OTA’s
open-loop gain must equal or exceed 64 dB. The circuit operates from a 1.8 V supply
and can use no more than 0.5 mA. The requirement on third-harmonic distortion to be
below -60 dBc (i.e. the third harmonic signal at the output is 60 dB below the fundamental).
You can assume having an ideal reference current and you are supposed to design
the current mirror biasing circuit to supply the current source transistor in the amplifier.
Recommended Steps for the design are:
1- Choose the right topology
2- Translate design requirements into circuit specifications
3- Design the OTA and the CMFB amplifier
4- Verify circuit performance.

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this a two stage amplfier:
first stage is a telescopic amplfier (bias =0.1mA), the second can be a common source (Bias=0.4mA).

but shouldnt the telescopic bias current be larger because it flows through many transistors ( 4 transistors per branch) while the common source current flows through only 1 transistor


also how to size the transistors ..... i dont know how to start


i also dont know whether to start by hand analysis or simulation .... plz give me advice

start by hand analysis. bias in the second stage must usually be larger for easy compensation. select currents, select VOD=0.2 for all transistors,and then find W/L. L=Lmin for the moment. estimate the size of the compensation cap. and then you have almost all you need and you can start to simulate it first for current bias (all transistors in saturation) and next AC response, and ...

I think a single stage OTA will be easier to design...

You may try folded or current-mirror topologies.

Sizing: start by an initial W/L guess. This is usually done by choosing the bias voltages and sizing transistors to achieve the desired swing. Then you will go through iterations to optimize. For example: to increase gain, increase L and keep W/L constant but then BW will suffer.

bas mesh elsingle stage hayeb2a makhno2 elswing beta3oo ? (0.3V for say 4 MOSTs y3ny 75mV lekol wa7ed?)

safwatonline said:

bas mesh elsingle stage hayeb2a makhno2 elswing beta3oo ? (0.3V for say 4 MOSTs y3ny 75mV lekol wa7ed?)

Click to expand...

that's exactly what i was thinking

bbbb said:

this a two stage amplfier:
first stage is a telescopic amplfier (bias =0.1mA), the second can be a common source (Bias=0.4mA).

Click to expand...

i just wanna ask one more ..... on what basis did you choose these bias currents .... is it just an initial assumption you made or it is based on calculation ?

i still cant understand why the telescopic branches get less current inspite of the long transistors stack .... :?:

i think the current distribution will depend on the GBW , so try to get an estimate value of the GBW u need then see what toplology u will use then distribute the current to get that GBW (with margin), note that u will need to take the phase margin in ur account , so to facilitate the compensation say that u will use miller then u need large gm2 to move the secnd pole apart and the dominant pole close (i.e. u need good current in 2nd branch) but to get a good gain BW u will need a large gm1 , so try to do some assumptions and make a primary design then re-adjust it on need (on simulator)

hey guys ,

i finished the design of the unity gain buffer with all the required specs ( 64 dB open loop gain , 0.5 mA total current ... etc )

except that on connecting the OTA as shown in the given circuit and making AC sweep i got the 0 dB curve extending till 45 MHz (unity gain buffer with Wu=45 MHz )

but when applying sinusoidal of 0.75v amplitude running at 40 MHz as required --> the o/p is too small ( not close to i/p in magnitude)
i.e differential input is 3V peak to peak while differential o/p is 1 v peak to peak

so why is this contradiction between frequency response and time response ?

also the 3rd harmonic distortion is very high ( 32 dBc not 60 dBc as required )

so plz guys help me

Because in both simulation you haven't established the DC voltage. If you probed the input terminals in the transient analysis, you'll find them to be 0v if the input devices are NMOS or 1.8V if the input devices are PMOS.

Try the following and see which one will help:
1. Set the initial condition on the input pair to the right value.
2. Connect both the input terminals to a large resistance (10M) to the proper DC voltage. you might notice a weired effect in the transient/AC simulation results because of that.
3. You mentioned that the OTA is to be used for a swtich cap design, why not simulate with the switches. You won't be able to do a meaningful AC simulation in that case though.

Added after 1 minutes:

One other thing to add, your load is 0.5pF perside, not 1pF, because each side has 1pF in the feedback in series with a 1pF at the input side.

I came too late..

Anyway, I would like to add something..

Generally, telescopic cascode gives high gain (powers of gm ro) , but low swing (because of voltage-headrooms needed to keep all transistors in saturation).. This is partially solved in the folded-cascode topology..

So, you can get more than the required gain using SINGLE folded cascode gain with CMFB..

Regardign AC simulation, remember that this kind of simulation is a LINEAR simulator, that's it can's show clipping or non-linear effects of circuits, moreover, before you run transient simulations, you would better to check prober common-mode biasing!

Hope that helps

Cheers,
--Knack