Typical IC Design interview questions

Hi all,

Can anyone share some examples of IC design interview Q&A?

Please give the example questions relate to R,L,C, CMOS, layout and digital.

many thanks.

asic design interview

There are quite a few threads on onterview questions on this site, you just need to search for them. Anyways, here is one that I was asked once:

Setup and Hold times, On what clock edge do you have setup time check and on what clock edge do you have hold tme check?

Ans: Setup on capture clock edge and hold on launch clock edge

interview questions static timing analysis

shahal said:

Ans: Setup on capture clock edge and hold on launch clock edge

Click to expand...

what do you mean bu Capture and Lanch?
May clearify this issue?

digital ic design interview questions

khaila said:

what do you mean bu Capture and Lanch?

Click to expand...

With pleasure. In digital systems, one of the criteria for timing is from flop to flop. So you have this flop which launches the data, it may pass through some combinational logic and is captured at another flop. Ideally, the time taken for the signal to traverse through logic and be captured at another flop is one clock period (this may be called the throughput of the system, please correct me here if I am wrong).

Having said that, the clock edge which launches the data is called the launch clock edge and the clock edge on the other flop which captures the data is called the capture clock. Delving a little bit deeper into this concept, after the launch edge of the clock the data needs to stay valid for a certain period of time for the flop to propagate the value to the Q pin of the flop. This is called the hold time of the flop. At the capture side, the data needs to be valid for a certain time at the D pin before it can be properly captured by the clock edge. This is called the setup time of the flop.

Hope this helped, and please do press the "helped me" button if it did. Cheers.

crosstalk + delay + victim

electronics_sky said:

Hi all,

Can anyone share some examples of IC design interview Q&A?

Please give the example questions relate to R,L,C, CMOS, layout and digital.

many thanks.

Click to expand...

you can get it on bbs, there are many of it

physical design, interview

tigerajs said:

electronics_sky said:

Hi all,

Can anyone share some examples of IC design interview Q&A?

Please give the example questions relate to R,L,C, CMOS, layout and digital.

many thanks.

Click to expand...

you can get it on bbs, there are many of it

Click to expand...

What is bbs?

digital ic design interview question

What is Signal integrity, Electromigration, Antenna effect?

How is signal integrity(SI) in related to Timing?
How does SI affects timing, how do u improve timing from SI effects?

What is CMP? how is it related to Timing analysis?

what is SSTA? what is onchip variation?

what are the challenges that u will face when work on technologies like 90nm, 65nm etc........

ic design delay concepts

au_sun said:

How is signal integrity(SI) in related to Timing?
How does SI affects timing, how do u improve timing from SI effects?

Click to expand...

Questions, questions and more questions. I will try to answer some, to the best of my knowledege. With shrinking technologies, what you get is a lot of cross coupled capacitance between metal layers. As a result of this, when you have a signal that is switching actively, it can induce a "cross talk glitch" or a "cross talk delay" on a "victim net."

Suppose, you have a net (agressor) that is being driven by a strong buffer. Its close to another net (victim) which is being driven by a relatively weaker buffer. Suppose at a certain time, our victim is going from high to low. Arround the same time, our agressor goes from low to high. The aggressor will than cause the victim switch from high to low a little later. Think of it as if the agressor prevented it from going from high to low, it just sort of pulled on it and prevented it from going low right away. What you now see is a delay on the victim net going from high to low, and further down the logic cone, this can cause failures. This is called "cross talk delay."

In another case, suppose the victim is low for some time now, and our strong agressor switches from low to high. This can and often will pull the victim net state from low to high for a short time, enough to cause a glitch on the victim net. Similarly, further down the logic cone you will see this glitch causing failures. This is called "cross talk glitch."

How to fix these. Well, lot of layout tools will take these into account when you start routing. You can tell your physical layout tool to leave adjacent routes of high frequency nets, like clock trees, to be empty. Once you have a routed database, you can get some sort of cross talk reports and then fix it in the layout tool. Two of the common methods I can think off would be to add stronger buffers to the victim nets (ofcourse that can affect your timing) or you could route the nets in a jogged formation so that the adjacent area between the victim and the agressor is comparatively less.

front end design, interview, ic

hey nice reply shalal ...
With increase in temperature net delay increases , and with increase in voltage net delay decreases ...
is it true ??
how should i understand this concept
thank you
Shiv kumar

interview question of static timing analysis

shiv_emf said:

hey nice reply shalal ...
With increase in temperature net delay increases , and with increase in voltage net delay decreases ...
is it true ??
how should i understand this concept
thank you
Shiv kumar

Click to expand...

Shiv thanks for the kind words. Unfortunatly, I do not know the theory behind the affect of temp/voltage on net delays. However, its easy to understand this concept using a "common sense" method.

By increasing temperature, you woud agitate the elctrons in a net and hence less electron will be available for cunducting current, hence temperature increase increases net delays.

By increasing Voltage, you have more power to drive the elctrons, hence net delays decreases.

This factor of temp/voltage increase or decrease is called K-factor. In many companies you can use this value to set factors to mimic increase or decrease of temp/voltage for best case or worst case simulation.

Best way to learn this would be to study on the net, I have found this forum to be a valuable tool for learning. You can also find a lot of articles online to study.

static timing analysis interview question

so same theory applies here as well ...
I am learning ASIC design as part of my curriculum ..........

can u tell me reason for non-linear increase in net LENGTH with Fanout

ex:
fanout ---- length
1 --> 2.0
2 --> 3.1
3 --> 4
5 --> 5.0
and later it is calculated using "slope"
thanks
shiv kumar

asic interview

IC Design Interview

Hi ,

This can be classified in to FrontEnd and Back End

1. Front End
Questions will be from basics to advanced about Digital Design ,
Timing Fundamentals ie Static Timing Analysis ( Setup , Hold voilations , Clock Skew , Logic Synthesis (ie Translation of your RTL to Netlist ) with user constraints

About in the BackEnd -->

Floorplan , Placement and Routing , Physical Verification ( DRC/LVS/ERC/ANTENNA) and some more.

1. These questions vary between a Fresh Engineer (Designer ) or Experienced Designer.

For Freshers : Refer to many books by Raebay, Naveed Sherwany , Wayne Wolf and many books on SoC.

You can find Problems in Mordern VLSI Design book - Wayne WOlf for Chip FloorPlan , and Power

The Book Digital Integrated Ckts By Raebay - refer for Electro migration and Power Planning problems.

BackEnd ( Post Layout Timing Closure, SI, CrossTalk, RTL Power/Gate Level Power Estimations,

Power Rail Planning ,

Finally the Physical Verification.

I hope these helps you.

ic digital design interview question

good questinos

interview questions and answers for ic design

hi, here is my collection of questiosns:
http://www.vlsiip.com/misc/q.html
Kr,
Ai

Re: IC Design Interview

rule of 3

Re: IC Design Interview

my collection of VLSI interview questions can be found at:

https://vlsifaq.blogspot.com

rgds
murali

Re: IC Design Interview

Hi.

Lots of questions and issues discussed in this forum. Make your digital basics strong.

Thanks

Re: IC Design Interview

i want to share some thing about how the temperature can affect the delays....
At lower temperatures the atomic sites of the material (what ever it is) would stay where ever they are. so an electron would see an vaccant area between the atomic sites and traverse freely.
At higher temperatures the same atomic sites of the material would be vibrating synchronously. now the electon see a wall instead of empthy spaces which is present in former.
That is how electrons get resisted more and leading to the delay.
hope this will help.
correct me if iam wrong.

Re: IC Design Interview

Hi Designers,

Almost more than 20 pages of VLSI/ASIC interview questions are compiled in the mentioned website. I strongly believe it would be worth your time to understand and appreciate the concepts of chip designing to build first pass robust Designs.

VLSI/ASIC Interview Questions Column:
https://www.vlsichipdesign.com/asic_vlsi_faq/faq_page1.html

Praise the Lord.
vlsichipdesigner
https://www.vlsichipdesign.com

IC Design Interview

1.How do u check whether our clock is reaching to all the paths ?
2.What is shrink factor ?
3. Is it possible to have zero skew in our design??
4.what is the difference between power analysis and rail analysis ?
5. Is it possible to have power bounce in SOC encounter??
6. Why u do power analysis?
7. How do u calculate the width of the stripes??
8.What was ur die size??
9. Instead of giving the power rings around the core area can i put it on the core area ? If yes then how???
These were the questions which was asked to me in the interview..............