engrbabarmansoor
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Can anyone clearly explain what is netlist and RTL?
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it's a list of interconnects at gate and predefined blocks level i think.research235 said:Hello Engrbabar
The top level design which generally u write in VHDL r verilog. can be RTL level .. but wen u sysnthesis this using synthesis tools like Design compiler we get a gate level netlist. which actually means a list of all interconnects at transistor level.
The RTL is teh top level entry ..
Please let me know if I am wrong ,
suresh