Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

What's the difference between "caseX" and "caseZ" in Verilog?

Status
Not open for further replies.
K

kunal1514

Full Member level 1
Full Member level 1
Joined
Dec 13, 2006
Messages
98
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
2,027
Hi All,

can anybody tell me wht's the difference between "caseX" and "caseZ" in verilog.

Also

priority casez(a)
3’b00?: $display("0 or 1"); //LINE -1
3’b0??: $display("2 or 3"); //LINE -2
default: $display("4 to 7");
endcase

what does the line "1" and line "2" explains
 

casez verilog

case statement compares 1,0,x,z ...
.......So in case of casez it treats all the values of z or which can also represented by ? as don't cares.

.......in case of casex it treats all the values of 'x' and 'z' as donot cares
 

verilog casex

for casez = it treats Z as don't care
for casex - it treats X n Z as don't care.

In ur code!
Line 1- LSB bit is don't care
Line 2- 1:0 bits r don't care

lets take an example
if a is 010 it displays 2or3
if a is 00x it displays 0or1
if a is 0zx it displays 0or1
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top