Question on the ESD protection failed test

cellphone said:

Hello chang,
suggestions/comments:
Are you relying only on the snap back action of the pmos/nmos for clamp action? Or do you have any separate RC based clamps in the circuit? Sometimes, diode based clamps' snapback voltage is very close to its breakdown voltage thereby not providing much help. You might wanna check the difference between the breakdown Voltage and snapback voltage. I also hope you have distributed the clamps evenly throughout the chip.
2. Are VDDA and VDDD (or GNDD and GNDA) two separate pins? If so, how come there are no back to back diodes between them to protect zaps from each other.
3. Reading your results:
a. you say that when there is a negative zap to gnda from the digital pin, I am assuming you negative zap the gnda pin keeping the digital pin to ground. This means that the ESD discharge path is from gnda to through the breakdown voltage of the clamp to one of the fwd biased PMOS protection diodes to the digital pins.
b. you say that +/- pulse between IOs did not pass. Meaning that the clamp is in the ESD discharge path in +/- zap.

My guess (if the layout is good enough, the ESD path is not a layouted out to have a a huge delay, and the diodes when fwd biased can take the current) would be that your clamp is the weak path in your ESd strategy. Like I said before, usually in a low voltage CMOS process, RC based time clamps are used to avoid the problems of having the MOS diode-breakdown and snap back voltage close to each other. Also, I dont know if you have many distributed clamps evenly throughout the chip. It usually is a good idea.

Did you decap the parts after zap to find out where the ESD damage has occured?

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cellphone said:

Chang,

I will try my best to you help you. I am writing quite a few questions. I dont expect you to answer them all to me. This is just to see if you have thought about all these ideas.
Questions/Comments:
1. Is GNDA and GNDD tied together when you do the ESD testing? Is it tied together anywhere internally in the chip? Or are they two separate pins? If they are separate pins, can you tie them together when you do the ESD testing?
[chang]they are seperate pins. Yes, we tried to tie them together.We do this test is to hope it pass, because they are in fact connected together in PCB. But, it failed again. The results showed that it is just contrary to the previous test. Still the same four pins failed. Three digital output pin which is the CMOS output and one analog pin. Three digital output pin did not pass the positive pulse to GNDA strike. And moreover, two of them did not pass the positive pulse to IO and one of them did not pass the negative pulse to IO.The analog pin did not pass the negative pulse of IO.


2. Did you separate all the pins and zap all combinations? If so, are the ESD failures consistant with what you are saying about the 4 pins failing?
My advise would be to have one part for each type of zap. This is because if you zap a part that is already zapped, it might fail prematurely as the part has already undergone stress.
[chang]we contracted it to another company for the ESD test. It is tested with called standard mode.I.e,the device is under test for one pin while connected all others together.

3. I do not see anything wrong with your ESD strategy except I do not know what the difference is between the snap-back voltage and breakdown voltage of the ESD clamp diode in your process. If they are not much different, the ESD clamp diode is not giving you much help as it is clamping close to its breakdown voltage which can be high (~7-8V) depending on your process. Usually I have used RC based ESDs for clamps and I usually space them evenly throuhout the chip. For e.g. in the last chip we did we required an ESD rating of 8kV HBM and we ended up using >25 clamps around the chip which was about 1.5sqmm.
4. For the combinations of the pins that are failing, please look at the ESD discharge path and compare it with the circuit discharge path and make sure the ESD discharge path acts before the circuit path can act. For this you'll have to know the breakdown and the snap back voltage of the ESD clamp diode.
5. I hope that the ESD ratings for the pins that are failing ESD are at least >500V HBM. Is this so? If this is true, can you convince your dept to go ahead with the current design? (I am assuming you don't have any or do not want to make any more changes in the design). Many times what I have seen is that the ESD ratings are over-rated. Does your application really need this high an ESD? And, is this a regular ESD spec (HBM or MM).
[chang]Unfortunatly, we test the ESD from 1000V, 500V step. The HBM >2000V, we hope to expect it to replace a product which has this spec.
6. When you did your DC measurements, did you check to see if the diodes from the output to Vdd and gnd are all intact and not damaged? In fact, I would recommend you check which diodes are intact to make sure that all the diodes can take the ESD current.
[chang]We again do the DC measurements for the second ESD test which tied the VDDD and VDDA,FNDD and GNDA together. This time also showed that the NMOS Tr failed.

7. It would be good if you could decap some parts to see where the failures occur.
[chang]But the cost exceed our capability.:-(
8. Although it is very difficult to see this effect in the simulation, if the breakdown voltages of the diodes are modelled, you can at the very least try to charge a cap (in simulation) to 2000V or whatever the ESD spec is and discharge it in the interested pin as you would in an ESD test and see where the resulting current goes. You will of course not see any damage in the simulation, but you might be able to see where the current path is.
[chang] we used the ggnmos as my clamp dioide. we are not sure if the breakdown model is included in spice/lib.

Do let me know how it goes. I'll be constantly checking. If you have more questions please do ask.

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