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VHDL "after" question

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ahmad_abdulghany

ahmad_abdulghany

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delay vhdl after

Hello,

I know that the "after" statement is not synthesizable in VHDL, then how to write a synthesizable "delay" statement to certain signal?

Thanks in advance,
Ahmad,
 

generate mesh vhdl

I guess you need to make a counter, and wait till it counts the number of clock cycles you want to delay.
That's what I use mostly.

Ragab.
 
depends, you can also use PLL, if you need delay your clock signal
 

after is only for simulation reasons
it's ignored by the synthesis tools
u should make a counter(up or down, down'll be easier to test its value of ZERO after the time elapses)
use a suitable clock frequency for all the delays u need
for each delay, see how many clock cycles it needs, and put this number in the counter
and whenever u need that delay, load the specified counter and start decrementing
and test it with zero at the end
 
To make "delay" of few nano to milli second u can use "WAIT" statement. There r three types in it
WAIT ON<signal name>
WAIT UNTIL<boollean exp>
WAIT FOR<time in nano sec>.
Hope this will clear ur doubt
welcoming comments
 
you can use a state machine to generate a delay you want depending your control conditions too
 
scorrpeio said:
To make "delay" of few nano to milli second u can use "WAIT" statement. There r three types in it
WAIT ON<signal name>
WAIT UNTIL<boollean exp>
WAIT FOR<time in nano sec>.
Hope this will clear ur doubt
welcoming comments
Click to expand...

But then again WAIT commands are not synthesizable!!
 
Thank you all for your helpful replies,
But i will add some inquiries,

Can i make certain design that's also synthesizable using drawn FSM, or truth table or other design techniques that we used to use in hand-design? without writing VHDL code? in other words, can VHDL tool generate certain accurate code for a design stated in terms of graphical design (FSM, truth-table, or whatever)??? If the answer was yes, I hope to know how...

On the other side, i thought that wait statement is as unsynthesizable as after statement! I can't imagine how can the tool generate wait statement and unable to generate after statement! Please clarify how can it be generated..

Salma, do you mean by "counter" is to make simple "for" loop (i.e. behavioural) and the tool will be smart enough to synthesis the correct counter (and the optimized in components?)

Iouri, is there any kind of PLL blocks in FPGAs? How to involve?

Thank you all,
Best Regards,
Ahmad,
 

SA Ahmad,

A for loop wouldn't ever be synthesized into a counter, that's for what I know.
The simplest counter can be easily made as follows:

Signal Count, Count_next : unsigned ( 3 downto 0) -- choose whatever size you need mesh lazem 3 akeed.
process (clk)
if rising_edge(clk) then
count <= Count_next;
end if;
end process;
Count_next <= Count + 1;

You may choose to add whatever conditions as Salma mentioned easily.
Good luck.
 
Ahmad Ragab,
I'm really unable to thank you :)

But unfortunately, i have another question..
If i was going to make a check on count=0, i think that i will use another if statement, my question is, will i use it inside another process? in other words, can i nest processes inside each other?

Also, can i replace the signal by a variable? i.e. will variable be also synthesized?

Jazakom alaah khayran :D
Ahmad,
 

SA Ahmed AbdulGhany,

About using "For loops" I want to clarify a small concept about it.

When you are writing your synthesizable HDL code, you have to use RTL (Register Transfer Level) abstraction Level. RTL is defined to be clock-by-clock behavioral description, i.e you describe the behavior of your hardware modules between two successive clock edges.

To do so, your code must be divided into Sequential Processes (which defines FF and Registers) and Combinational Processes (which gives logic to hardware modules).

So, according to the definition of RTL as clock-by-clock behavioral modeling, you can use behavioral modeling in Combinational processes (for loops and so) but do not forget that this combinational logic will be all done within one clock cycle while the data is being transfered from one register to the next one.

I hope i made this concept clear.

Good Luck
Yasser,
 
salamo alikom ahmad,

for different delays u can have an enumerated type (delay_type)
then u can make a signal from this type (delay)
use a natural signal for the counter (count)
and for testing the different conditions u can have case statements
to load the required type of delay in the counter according to the state of your machine
and u can have one of the values for ur delay_type that is called like: no_op
and in its case statement u can make if loop to see if the counter is zero or not
if it's larger then decrement it (count<=count-1; but it has to be natural of course)
if not then it'll go out of the process and then enter it again upon the next clock
(but this goes of course if there are no interruptions for setting a new value of a delay)
so u can have two processes
one sequential for the counter
and one combinatorial for the rest of the design (to give values to all signals according to the state of ur machine)

the after and wait aren't synthesizable
they are just for functional simulation

i hope i helped in some way
never hesitate to ask more
Regards,
Salma:)
 
can not we cascade even no. of not gates and then take the signal out.....
now using CRO we can check the signal delay.....(in case of fpga...).

cant we do????
 

Guys ..

A concept .. you can never model a synthesizable arbitrary delay using HDL .. in other words, you can't model a delay equal to a part of a clock cycle ( in case of sequential ccts ) .. or a part-of-circuit delay ( in case of combinational cct ) ..

All circuit delays are function of the technology library provided by your fab. To clarify this point, what if you want to use TSMC .13 u technology after u have been using .35 u ? .. should you change your RTL ? ..

Delays are only used in case of modeling inside testbenches ..

On the other hand .. a delay of integer multiples of a clock cycle is simply acheived by a counter as people said .. or if u want a delayed copy of a certain signal you only have to do this :

if rising_edge(clk) then
x <= y;
end if;

where y is the original signal .. and x is its delayed copy. You can always put that in a seperate clocked process not to conflict urself with other things ..

Moreover, HDL simulators these days offer to give you a fake delayed signals in case u see them useful in ur simulations .. like if u want to easily compare one signal's current value with some of its history all along the test duration.

hope this helped
 

hirs my code for a delay clock..
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY clk2 IS
PORT (
   clk : IN STD_LOGIC;
   clkkj : OUT STD_LOGIC);
END clk2;

ARCHITECTURE a OF clk2 IS
BEGIN
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 4096;
BEGIN
   IF (clk'EVENT AND clk = '1') THEN
   cnt := cnt + 1;
   END IF;

   IF (cnt >= 2048) THEN
   clkkj <= '1' ;
   
   elsif (cnt >=4096) then
   cnt := 0 ;
   ELSif (cnt <= 2047)  then
   clkkj <= '0';
   
   END IF;

END PROCESS;
END a;
if you could see it...
for 4096/2 a pulse is genarated...
this represent a delay for a 25Mhz which is a clock on a xinlinx spartan3
a default clock.
 

leoren_tm said:
hirs my code for a delay clock..
Code: 
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY clk2 IS
PORT (
   clk : IN STD_LOGIC;
   clkkj : OUT STD_LOGIC);
END clk2;

ARCHITECTURE a OF clk2 IS
BEGIN
PROCESS (clk)
VARIABLE cnt : INTEGER RANGE 0 TO 4096;
BEGIN
   IF (clk'EVENT AND clk = '1') THEN
   cnt := cnt + 1;
   END IF;

   IF (cnt >= 2048) THEN
   clkkj <= '1' ;
   
   elsif (cnt >=4096) then
   cnt := 0 ;
   ELSif (cnt <= 2047)  then
   clkkj <= '0';
   
   END IF;

END PROCESS;
END a;
if you could see it...
for 4096/2 a pulse is genarated...
this represent a delay for a 25Mhz which is a clock on a xinlinx spartan3
a default clock.
Click to expand...


You just need to keep in mind that this counter is huge and you need to keep track of the synchronization issues .. it's also quite unwanted to use a binary counter of this length .. you better go for a gray code solution ..
 

uhmmmmmmmmmmmmmm......
can you modify it???
yes i have a problem on my simulator...
it realy slow down...
im a newbie on VHDL
 

effectively what you have done is not called a DELAY .. this is a generated slower clock ..

There are some good documents on generated clocks and clock division algorithms .. try the one is this link :

h**p://

I believe it's comprehensive.
 

ah ok ...thanks..
i want to divide my clock...but for a reason, i got problem on doing it on a clock divider, so i made use of the process..
which realy not a good implementation, it realy got a good bit on my speeed...
thanks for the sugestion...anyway..
its my month on doing a VDHL programing...
maybe lot of thing i have to study...
any good book???
i got a CPLD book and aplication...
any sugestion?
 

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