ahmad_abdulghany
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delay vhdl after
Hello,
I know that the "after" statement is not synthesizable in VHDL, then how to write a synthesizable "delay" statement to certain signal?
Thanks in advance,
Ahmad,
Hello,
I know that the "after" statement is not synthesizable in VHDL, then how to write a synthesizable "delay" statement to certain signal?
Thanks in advance,
Ahmad,