KaiZX
Junior Member level 1
oscillator cd4007
I originally posted a question here. **broken link removed**
That question was asked in relation to a project I'm doing that requires breadboarding. As it turns out, I also need a clock generating circuit for a different, ASIC design project I'm doing. Because this time I'm doing ASIC design, I do not have the option of using a crystal oscillator. Rather, I need an oscillator only FETs and passive elements (resistors and capacitors).
There're two goals I'm aiming for: low current draw (preferably a few uA), and robust design across a fairly wide Vdd range.
I've already investigated the possibility of a ring oscillator, but I've ruled out that possibility. The main reason is because of Vdd instability. So instead, what I'm doing is a bastardized version of the LMC555 timer, except with some additional modifications. I'm using are simple diff-amps as comparators (this is in direct relation to a post I made earlier about T-spice analysis **broken link removed**). I also have a buffered stage seperating the output from the RC feedback, to prevent the output from being loaded down by the resistor.
The main current drain is the voltage-divider network. In an IC package they're fine, but in my current design they can drain up over 0.1mA, and that's totally unacceptable. My quick fix is increasing the resistor values. My comparators also draws fairly large current.
Are there any ideas for improvements to my ideas? I'm also definitely interested in alternative design ideas.
Thank you in advance.
I originally posted a question here. **broken link removed**
That question was asked in relation to a project I'm doing that requires breadboarding. As it turns out, I also need a clock generating circuit for a different, ASIC design project I'm doing. Because this time I'm doing ASIC design, I do not have the option of using a crystal oscillator. Rather, I need an oscillator only FETs and passive elements (resistors and capacitors).
There're two goals I'm aiming for: low current draw (preferably a few uA), and robust design across a fairly wide Vdd range.
I've already investigated the possibility of a ring oscillator, but I've ruled out that possibility. The main reason is because of Vdd instability. So instead, what I'm doing is a bastardized version of the LMC555 timer, except with some additional modifications. I'm using are simple diff-amps as comparators (this is in direct relation to a post I made earlier about T-spice analysis **broken link removed**). I also have a buffered stage seperating the output from the RC feedback, to prevent the output from being loaded down by the resistor.
The main current drain is the voltage-divider network. In an IC package they're fine, but in my current design they can drain up over 0.1mA, and that's totally unacceptable. My quick fix is increasing the resistor values. My comparators also draws fairly large current.
Are there any ideas for improvements to my ideas? I'm also definitely interested in alternative design ideas.
Thank you in advance.
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