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Fixing Setup & Hold Violations

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carrot

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hold time violation

Hi,

How to fix Timing Violations(Setup & Hold time Violations)?
What are all the things that has to be taken care while fixing it?
 

setup time violation

Setup Time: the amount of time the
synchronous input (D) must be stable
before the active edge of the clock
Hold Time: the amount of time the
synchronous input (D) must be stable
after the active edge of the clock
If either is violated correct operation of the
FF is not guaranteed Metastability can result.

Below links are useful
**broken link removed**
http://www.vlsibank.com/sessionspage.asp?titl_id=6822
http://www.syncad.com/pdf-docs/paper_cc_timing_everything_2003.pdf
 
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    vnnavy

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setup and hold time violation

Hi,
Setup time fixing:
1) reducing combinational logic delay by minimising number of logic levels
2) splitting the combinational logic
3) Implimenting Pipelining
4) Using double syncronizer using flipflops
Hold time fixing:
1) Can be fixed by adding delays on input ports
2) adjusting clock speed

Generally hold time is not in the user control

Thanks
 

set up and hold time violations

hi
if u find the violations after the tape out
then u can find a work around solution by playing with working temp
 

hold time violations

During the initial iterations only set up violations are fixed whereas hold violations are fixed only after the actual physical place and route info is available. Set up and hold violations are mutually exclusive. set up violations can be fixed by reducing the combo delay. Hold time violations are fixed by increasing the combo delay or by inserting buffers such that it does not cause the setup violations. Increasing or decreasing delays by upsizing or downsizing the cells ripples back into the design and the whole design is to be taken into consideration for carrying out the STA again.
Cheers:)
 

    V

    Points: 2
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fixing setup and hold violations

satyakumar said:
Hold time fixing:

2) adjusting clock speed

Generally hold time is not in the user control
Click to expand...

Hold time is independant of clock speed which makes it a potential design killer. No matter how much you slow your clock you may still have hold violations. They are easily fixed by inserting buffers or downsizing cells (but making sure not to create any setup violations). Also a good idea to add some extra hold margin.
 
setup and hold violations

Hi,
By adjusting Clock speed u can vary setup window margin, and after one can insert delays are buffers to fix hold violation. By adding delays to fix hold time doesn't solve problem, setup and hold time are interdependent.

There is no fix for hold vioaltion in RTL rather then adding delays.
 

hold time violation example

hi carrot
hold and set up violations are mutually exclusive and vilations can be adjusted with the combi delays and these delays will be more if u increase working temp and will be less if u decrese temp ..just this is my thoguht please suggest me whether its possible in real time or not and tell me if there is any problem with playing temp
 

hold violations

But in real time operation, we can't fix temp. working temp is indepedent
 
setup and hold time violations

when fix setup/hold:
please analysis whether the violation is caused by clock skew, if yes ,adjust it.
 

setup hold time violation

Insert high and low drive strengths in failing paths
 

how to fix hold violations

carrot said:
Hi,

How to fix Timing Violations(Setup & Hold time Violations)?
What are all the things that has to be taken care while fixing it?
Click to expand...


Hi ,

Setup violation can be fix by insert registers in worst path.
Holdup violation can be fix by insert buffer.

Thanks.
 

fix hold time violation

whhen setup time time violates your design works with lesser frequency but when you hold time violates your design doesnt work at all.thats why hold time fixing is critical.
You can fix setup time time by adding some dalay by adding register or you can adjust the verilog coding.
if else loops are replaced with case statements.
 

how to fix setup time violation

atuo said:
Holdup violation can be fix by insert buffer.

Thanks.
Click to expand...

Can one identify those cells either :
* inserted by insert_buffer command, or
* auto buffer insertion by DC during optimizations ?

Perhaps there is a special attribute on those cells ?
 

In one of my projects

I have got timing violations for a same register at different times. I wanted to know if though the timing violations are at different times, fixing one would fix the other violation at different time also right?
 

bobjee said:
In one of my projects

I have got timing violations for a same register at different times. I wanted to know if though the timing violations are at different times, fixing one would fix the other violation at different time also right?
Click to expand...

Hi Carrot,
After manufacturing of chip, if you are getting hold violation. then it will not work. But still if you want to make it work, go to lab, increase the lab temp depending on your hold time violation, since hold violation is inversely proportional you can make it work.
 

Hi , can anyone explain Negative Values in Setup and Hold Checks?
 

Re: hold time violation example

raju3295 said:
hi carrot
hold and set up violations are mutually exclusive and vilations can be adjusted with the combi delays and these delays will be more if u increase working temp and will be less if u decrese temp ..just this is my thoguht please suggest me whether its possible in real time or not and tell me if there is any problem with playing temp
Click to expand...

How can you play with temp. after taping out?? its not in your control...can you please clarify your ans?

During STA we can take temp. to consideration but how after tape out?..

---------- Post added at 11:24 ---------- Previous post was at 11:21 ----------
prpatil03 said:
Hi Carrot,
After manufacturing of chip, if you are getting hold violation. then it will not work. But still if you want to make it work, go to lab, increase the lab temp depending on your hold time violation, since hold violation is inversely proportional you can make it work.
Click to expand...

I dont think chips are made to work in labs only either.... so I would say leave out temp. and playing with temp. to fix any violations....best is to increase/reduce datapath delay or to introduce skew to clock path...
 

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