ahmad_abdulghany
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Hello all,
I'm using VHDL to model certain communication system, and i don't know which sentence of the VHDL syntax i use can be synthesized and which cannot, how can i be sure of them?
I need a tutorial about the FPGA flow starting from writing VHDL code down to burning to the FPGA chip... can anyone help me regarding that?
Thanks in advance,
Ahmad,
I'm using VHDL to model certain communication system, and i don't know which sentence of the VHDL syntax i use can be synthesized and which cannot, how can i be sure of them?
I need a tutorial about the FPGA flow starting from writing VHDL code down to burning to the FPGA chip... can anyone help me regarding that?
Thanks in advance,
Ahmad,