help: how to simulate Vos in a comparator?

I am simulating a latched comparator, how can i simulate the offset voltage of it?
I used the 018 lib and simulated under "mc"(monte) situation which include the default Monte Carlo parameters, is it enough?
How can i get Avt, Ak, Abeta and other parameters ?
Thanks a lot!

someone tell me to make the mosfet a subcircuit and add the monte parameter in it, but how can i make mosfet a subcircuit?

Offset usually happens when you have mismatched devices. So, if you run a regular simulation with all devices ideal, you should not see an offset at the input of the comparator (input-referred offset). So, to know how much offset the comparator has, you have to introduce a mismatch in the devices.
Mismatch is usually done to; Vth, L and beta of the transistor. If you know the values of those paramter that will procude the worst case scenario, you can change your netlist manually and run the same regular transient simulation. This is usually NOT done, because you usually don't know the values that produce the worst case scenario.
The other way is to do it though montecarlo.
For montecarlo, you need to specify how many sigma variation of the above paramters you want the simulator to mismatch them and the simulator will do the rest.
The output of the simulator will be different for different simulators.
To know the input and output format of MC (montecarlo), you need to consult the manual of your simulator.

Hi, analog_guru, thanks so much
i used the mc lib and the default parameters to perform a 3-sigma monte carlo simulation, the result is so good, not as high as i thought be.
so i think maybe i should make the mosfet a subcircuit and set Vth, L and beta in it to perform a simulation, but how can i make it?

I assume you know how to make a subcircuit in hspice or spectre.
In order to be able to introduce a change in Vth of a certain transistor, you build a subcircuit that has that transistor in it. Connect a DC source to its gate. The effective Vth will then be the intrinsic Vth in addition to whatever your DC voltage you are adding to your gate (pay attention to the sign of the DC voltage).
To model the beta, I think you can add a vccs in parallel with your transistor, so, its output current is added to the drain current of the transistor.
I am not sure how to model the L change within the subcircuit. Someone else (especially modeling guys) can help here...

thank you very much, i will try
and do you konw how to set Vth, L and beta param in mosfet?