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Help Required - Xilinx Spartan 3 Kit

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adilsaleem

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Can somebody please figure out what can possibly be wrong with code ?

I compile and synthesize it in Xilinx 6.1 for Spartan 3 kit, after synthesis it shows all the I/Os in the RTL schematic. But when i try to map it on the FPGA using .ucf file it does not recognize inputs and give error
 

What is the error message?
What's in your UCF file? We may need to see your HDL files too.
If you don't use a UCF file, does it complete without error messages?
Are you able to build other projects successfully, or is this your first project?
 

This is not my first project, i have been using it for quite a while.

The .ucf file give error "no net(s) found" for the lines where i have specified the inputs.

I think .vhd files are not allowed to be uploaded here. I'll try to mail it to you.
 

Try to figure out what's different between your previous successful projects and your current troublesome project.

I'm a Verilog guy, so I may have trouble using your VHDL. However, someone else can probably help you.

If your VHDL and UCF are very short, you can paste them into your message with "code" tags to make it easier to read. Or you can zip up a few small files and attach it to a message.
 

Hi adilsaleem, I had no problem synthesizing your VHDL and UCF files. All your UCF pin assignments worked fine. Maybe your ISE project settings are incorrect, or maybe you have a broken version of ISE. I'm using ISE 8.1.03i.

I selected target device 3s200-4-ft256.

You need to assign a pin number to 'clk'.
 

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    adilsaleem

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