staraimm
Full Member level 2
hi, anybody, I wrote the verilog code as follows.
module test(inclk, inclr, indata, outclk, outclr, outdata);
input inclk, inclr, outclk, outclr;
input[7:0] indata;
output[7:0] outdata;
reg[7:0] mem[0:31];
reg[4:0] memcnt;
always @ (posedge inclk or negedge inclr)
begin
if(!inclr)
memcnt <= 0;
else
memcnt <= memcnt + 1;
end
always @ (posedge inclk)
begin
mem[memcnt] <= indata;
end
reg[4:0] rdcnt;
always @ (posedge outclk or negedge outclr)
begin
if(!outclr)
rdcnt <= 0;
else
rdcnt <= rdcnt + 1;
end
assign outdata = mem[rdcnt];
endmodule
Assume the inclk is about 15Mhz, and the outclk is about 10Mhz. I compiled the code with the QuartusII web version. But in the first 8 clock, I can't get the correct data on the bus. Can anybody tell me why? Thanks.
module test(inclk, inclr, indata, outclk, outclr, outdata);
input inclk, inclr, outclk, outclr;
input[7:0] indata;
output[7:0] outdata;
reg[7:0] mem[0:31];
reg[4:0] memcnt;
always @ (posedge inclk or negedge inclr)
begin
if(!inclr)
memcnt <= 0;
else
memcnt <= memcnt + 1;
end
always @ (posedge inclk)
begin
mem[memcnt] <= indata;
end
reg[4:0] rdcnt;
always @ (posedge outclk or negedge outclr)
begin
if(!outclr)
rdcnt <= 0;
else
rdcnt <= rdcnt + 1;
end
assign outdata = mem[rdcnt];
endmodule
Assume the inclk is about 15Mhz, and the outclk is about 10Mhz. I compiled the code with the QuartusII web version. But in the first 8 clock, I can't get the correct data on the bus. Can anybody tell me why? Thanks.