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why ESD protection needn't in test pad and probe pad?

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hktk

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When reading "The Art of Analog Layout (Sencond Edition)", it said that ESD protection is not needed in test pad and probe pad because the are encapsulated in package after assembling, but when testing the chip before assembling, whether the test pad and probe pad suffer ESD from probes? why ESD protection needn't in test pad and probe pad?

Thank u for your answer.
 

i think (IMHO) during probing, the wafer is very well insulated. no path for ESD zap
 

ESD Zaps occur when there is a build-up of charge on an insulating material.

Probes are conductive pieces of metal, connected to a well-defined voltage source. The wafer is not subject to an ESD zap during probing.
 

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    hktk

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    Alperro

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esd affair is stochastic,but the probe or test work are in ready,without esd protection can reduce the area.
 

a test environment can be carefully controlled to avoid possible ESD hazards, by using well grounding of human boday and probe tips, there is no potential ESD risk, as long as those pads are not bond out to package level, they are safe.
 

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    hktk

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the test pads and probe pads without esd protection need a proper test environment.
 

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