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How to implement 1 to 4 demultiplexer in VHDL

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Rfboy

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Hi guys,
I need to implement a simple 1 to 4 demultiplexer in vhdl...please help me ithis is the my first time in vhdl !!!!!
The input and output are a byte and the selector are a line with 2 bits...

Thak you
 

vhdl demux

reference

**broken link removed**
 

vhdl demultiplexer

1 to 4 demultiplexer

**broken link removed**
 

demultiplexer vhdl

You can see some ideas in:

**broken link removed**
 

demultiplexer vhdl code

Its very simple...

Code: 
library ieee;
use ieee.std_logic_1164.all;

entity demux is
  
  port (
    D0  : in  std_logic_vector(7 downto 0);
    D1  : in  std_logic_vector(7 downto 0);
    D2  : in  std_logic_vector(7 downto 0);
    D3  : in  std_logic_vector(7 downto 0);
    SEL : in  std_logic_vector(1 downto 0);
    Y   : out std_logic_vector(7 downto 0));

end demux;

architecture behave of demux is

begin  -- behave
with SEL select
  Y <= D0 when "00",
       D1 when "01",
       D2 when "10",
       D3 when "11",
       (others => 'X') when others;
end behave;
 

demux in vhdl

Hello !
I think that the code posted by nand_gates is a mux not a demux.
A demux has 1 input and 4 outputs and the input is connected to the output selected by selection.
 

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8 bit 1: 4 demultiplexer vhdl code

Hi guys, we are posting replys to this thread although it was created 3 years ago :D

any way I think one way of creating a 1 to 4 8bit demux is as follows :

Code: 
entity demux is 
  
  port ( 
    D   : in  std_logic_vector(7 downto 0); 
    SEL : in  std_logic_vector(1 downto 0);
	 Y1  : out  std_logic_vector(7 downto 0); 
    Y2  : out  std_logic_vector(7 downto 0); 
    Y3  : out  std_logic_vector(7 downto 0); 
    Y4  : out std_logic_vector(7 downto 0)); 

end demux; 

architecture behave of demux is 

begin 
process(D,SEL)
begin
case SEL is				 
when "00" => 
	Y1 <= D;
	Y2 <=  (others => '0');
	Y3 <= (others => '0');
	Y4 <= (others => '0');

when "01" => 
	Y2 <= D;
	Y1 <= (others => '0');
	Y3 <= (others => '0');
	Y4 <= (others => '0');

when "10" => 
	Y3 <= D;
	Y2 <= (others => '0');
	Y1 <= (others => '0');
	Y4 <= (others => '0');

when "11" => 
	Y4 <= D;
	Y2 <= (others => '0');
	Y3 <= (others => '0');
	Y1 <= (others => '0');

when others => null;
end case;

end process;
end behave;

in this demux when an output is not selected it will provide a zero, if you need to preserve the last output just delete the Y# <= (others => '0'); , this of course will generate latches at the outputs.
 

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