Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

clock domain crossing and synchronizing

Status
Not open for further replies.

sree205

Advanced Member level 1
Advanced Member level 1
Joined
Mar 13, 2006
Messages
453
Helped
58
Reputation
116
Reaction score
25
Trophy points
1,308
Activity points
4,420
Hi,
Could anyone tell me some methods of synchronizing control signals which cross clock domains ? i only know of double flopping the signal. even after that if it leads to metastability, what else can be done?
 

Following document is very useful before you r looking for a synchron
 

thanks for the link. i've already gone through that document. I'm specifically looking for multi-stage synchronizers and their impact on MTBF.

Thanks !!
 

Sree,
Since you already know about the MTBF, a two stage synchronizer itself has a pretty good MT. Generally the rule of thumb is that the metastability resolves itself in a time period around ~20Th/su. So as long as your frequency isn't the limiter (ie. freq of operation is 20Th/su) a two stage synchronizer should do. In practically applications (systems designed at Ghz) we use a 3 stage synchronizer.
Much of what we contemplate here is just an educated guess any engineer makes at the expense of solid understanding of reliability.

-B
 

    sree205

    Points: 2
    Helpful Answer Positive Rating
Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top