RFIC Design flow : Some doubts ???

rf ic design procedure

Hi.
I want to know about RF design flow.

I know from my friends in Industry that in standard IC flow there is circuit designer and layout engineer. Circuit designer designs and that design is been layouted. Then this layout gives netlist with parasitics which is then used for simulation and then they have some iteration before they arrive at final performance.

Is it not similar in RFIC design ?
As I understand, I will need RF Design tool to give complete specification of modules. These modules will be given to circuit designer. He/she will give the design to layout engineer and then again we will have some iteration like in IC design. This schematic and layout can be designer using schemaic editor from Cadence / Synopsys tool chain. So, there is no role of RF design tool other then defining specification.

Please correct me as I might be wrong ?

It can also happen that System designer can give specification which when implemented might come out to be unacheivable, so again new set of specification will be releases which can delay the whole project.
How can this be avoided ?

Thanks for your response..

rfic specification

For RF IC design flow, you're almost right.
The role of the system design and tools depend on skill of designers.
Let me give you an example:
-it is possible to use spreadsheet to give specification of each block, design ans sim. schematics , layout & post layout sim. then proto and measure.
-or spreadsheet/matlab/ptolemy...-> circuit design (schematic, layout, postlayout sim)-> back to ptolemy (for example co-simulations in ADS)-> prototype & verification.

The most effective path should be chosen. But what is the most effective path? It depends strongly on skill/experience of the system/circuit/layout designers, on project complexity and cost for the project (licenses/manpower/masks/prototypes/lab...).

You surely see the difference between an analog AM radio and a multistandard single chip (RF+BB) tranceiver for cellular applications for example.

So the answer for your second question is that cooperation between different designers is really important. In particular system eng. should define the RF IC performance together with circuit designer (or better have directly experience in circuit design).

I hope it can help.

Mazz

site:edaboard.com rf ic layout

thank you Mr MAZZ for explanation
Can you give me some links in order to argument your respense ?

Sorry, no link.
Only direct professional experience.
Mazz

actually the rfic designers supervise the layout,and some times they do it themselves especially in some small company,and I think the latter is better while the first is more effective.

Thanks a lot for your replies. But what baffles me how does RFIC specification will start ?
Suppose I I have to make WiMAX RFIC, which is completely new chipset which require new bandwidth and gain requirements and all other previous designs that system designer might have done.
What will be step by step procedure for this design ?
How will the first specification will be framed ?

Hi;

can anyone give us one specification example ?

First you have to link the limitations of an architecture in mind with the system specs. If you take for example WiMAX these will be

RX Sensitivity
Adjacent/Alternate Channel Rejection (LowLevel+HighLevel)
TX EVM Budget Distribution
RX/TX Frequency Stability
Implementation of the AFC

The most important point is that have to be very experienced to not miss any critical system parameter in the implementation. If you miss any you have the risk of rework some manyears of designwork while done the implementation. Because some of the circuits used for implementation are not existing before you have to exactly knowledgeable about circuit/technology limitation.

In WLAN for example it took some years before a good sheme was worked out to overcome DC offsets within a fraction of a preamble symbol.

WiMAX is a significant higher player than WLAN. The EVM is not far away from th best signal analysers, the RX/TX frequency stability must be in the part per billion range, there are many bandwidths and frequencies. This will trigger a learning curve so that WiMAX is not a derivation from WLAN. If want to train topdown development take some infos from the net about WLAN chips sets. Patents are also usefull.

Well, you can mostly derive all of the block level specifications from the Protocol specification. Here is a procedure.

1-Read the entire specification. Make note of everything that seems to be radio performance related. For example, adjacent channel interferer, Maximum input power, minimun input power, channel changing time, etc.

1a- Make an assumption as to the receiver architecture you will use. Dual conversion, single conversion, direct conversion, etc.

2-Start calculating what you can. For example, From the minimum input power, you can derive the Maximum Receiver system noise figure. From the Adjacent channel interfer, you can calculate the LO Phase noise, the Channel filtering specifications, and the A/D Converter bit width. A two tone interfer test will give you a receiver linearity specification.

3-Once you have specifications for the receiver as a black box, you can go in and distribute the gain/Noise figure/Filter Bandwidth/Linearity through the system as you see fit.

4-Share the block level specifications with the IC design team.

5-Once they have stopped calling you an idiot for specifying impossible blocks, ask them what they can design.

6-Go back to your gain distribution, plug in blocks that you can build, and then re-do the design.

7 Repeat 4, 5, and 6 until everyone is happy.

Here are a couple of papers that my prove helpful.