Guarding with protel DXP 2004

protel capacitance stray

Hello, I'm trying to guard some high impedance nets that have sub nano ampere currents in Protel DXP 2004 for a 2 layers board. I can create polygons in the sensitive area and attach the polygon to a high quality follower of the sensitive net but it is not satisfactory. Some areas of the polygons can't be attached to the rest of polygon because of geometrical and routing constrains and they are removed when I remove the dead copper. So some areas are not guarded. Second question is about the stray capacitance between sensitive net and guarding net. I am worry that if guarding net becomes to close to the guarded(sensitive) net the stray capacitance may worsen the situation because as I said input impedance of the sensitive net is very high(as high as 1 GOhm) and noise may be flowed to the guarding net and creates some noise current. How can I retain stray capacitance between guarding net and guarded net at acceptable value? So I have two questions
1- How can I create Guarding nets in Protel DXP 2004?
2- How can I maintain stray capacitance between these two nets at acceptable values in this software?

Thank you very much in advance.

remove dead copper protel

1. Try giving the polygon different net name from the rest of the polygons. If net name is the same the polygon 'island' will be removed when pouring Cu. Guarding the polygon can be done by creating a dummy tracks around it.

2. Not that I know of - but as rule of thumb keep the gnd net away from the sensitive one. However it depends on the characteristics of the net itself -ie freq, current, z etc.


Protel user

high impedance nets may cause leakage

Hello dindes,
1- I don't want to create dead copper to protect the sensitive net. I was trying to explain why using a polygon to guard a sensitive net is not a good idea. A dead copper area can't guard the sensitive net and it is better to be deleted. Ideally I like to route a guarding net at both sided and beneath of the sensitive track all the way. It is extremely painstaking to do this by hand so I used the polygon but as I explained it is not satisfactory too. is there any trick or rule so I can route a net(the guarding net) in parallel with the sensitive net in all of its path and also guard through hole pins with that guarding net.
2- About keeping impedance at desirable level I have seen some rules for this but I'm not sure how should I use them. I think (never have done it) protel can keep impedance of two routed nets at a desirable value.
Thanks

polygon dxp

You are looking at the problem backwards. You are concentrating on the sensitive traces when you should be looking for the possible aggressor traces or sources. Once you have identified the potential sources of EM "noise" or dielectric current leakage you can avoid them with your sensitive traces. Proper routing, rather than blindly placing "guards" is the preferred solution.

The purpose of a guard trace is to separate a sensitive trace from an aggressor source. As a general rule of thumb, if you keep the distance betwen parallel traces at least 3x the trace width, you can maintain less than 50db EM coupling. Using the right dielectric, in combination with coatings and physical separation, will prevent leakage current problems. If you have properly routed the board, guard traces become unnecessary. In fact, they may actually act as coupling traces and degrade your sensitive signal as you have noted with your concern about capacitance.

You SHOULD note that any return path copper near your sensitive trace will lower its characteristic impedance. You say that the traces with which you are concerned are "high impedance". Any connected copper within 3x-4x the width of the trace will be "seen" by your sensitive trace inductively and capacitively, and will lower its impedance. The closer the copper, the lower the impedance and the greater the coupling.

Guard rings and guard areas are often necessary on a semiconductor die to drain leakage currents. They are unnecessary on a properly designed printed circuit. They can create problems rather than solving them.

There are many texts and papers on the subject of guard traces. One such article can be found at: https://www.altera.com/technology/signal/columns/2006/2006-10-oct_1.html

Guarding with P*otel DXP 2004

Hello House_Cat, thank you very much! The link was very informative. It really made me to think seriously before applying any kind of guarding. But two important issues remain:

1-Because PCB is placed inside a shielded enclosure, outside sources of noise have not been appreciated it the article reasoning but when the signal leaves the device it has to be shielded somehow. I think shielding with ground is not a good option for me because the potential difference(sensitive net has a voltage range between 1V and -1V) may cause current leakage at this level of impedance(~ 1GOhm)
2-In some areas still I think guarding will be necessary. For example when the high impedance signal enters the Opamp(Pin3) it is inevitably near Pin 4 which has about -15V and as the distance inevitably is less than 100 mil(pin thickness + 2 pad radius) it can cause considerable leakage. So it has to be guarded.

Thank you very much again!

With regard to your two points:

1. For your circuit, I would definitely place the board in a shielded enclosure. The enclosure should be "grounded" to your circuit power supply common. What you want to do is provide a return path for induced current, but you want it to be somewhere else but your sensitive trace. The way to do that is to surround the circuit with a well grounded cage.

2. For your nearby "high" voltage pins, you could simply place a short "ground" trace stub between the sensitive pin and the "high" voltage pin. That would give leakage current a return path other than your sensitive pin. The trace can be thin and should be short - its only job is to provide a drain for leakage current to keep it away from your protected pin.

I used quotes around the term "ground" above because it is a general term for whatever the common voltage reference is for your circuit board.

In both cases, the goal is to provide stray fields and current with a lower impedance (hence easier) path than your sensitive trace or pins. The current will flow somewhere, it's your job to make it flow where you want.