dsula
Newbie level 4
Hi,
I have an NMOS diff-pair that exhibits a certain offset. This offset is dependent on the input common mode. I have a hard time explaining this effect. Anybody knows? How can I avoid this? I don't care much about the offset of the diff pair, but I care about the offset not to change across a large common mode input range.
Or to give you some numbers. (The diff pair is used in a unity gain single ended miller op-amp)
I bias the inputs to 2V and I measure 5mV at the output.
I short the inputs to 3V and I measure 8mV at the output.
Thank you all for any thought on this.
ds
I have an NMOS diff-pair that exhibits a certain offset. This offset is dependent on the input common mode. I have a hard time explaining this effect. Anybody knows? How can I avoid this? I don't care much about the offset of the diff pair, but I care about the offset not to change across a large common mode input range.
Or to give you some numbers. (The diff pair is used in a unity gain single ended miller op-amp)
I bias the inputs to 2V and I measure 5mV at the output.
I short the inputs to 3V and I measure 8mV at the output.
Thank you all for any thought on this.
ds