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U will have the option of performing parasitic extraction using virtuoso if u have the needed rules files like diva, dracula and other ,,, some use mentors calibre for this .. so check wat u ahve and perform acccordingly for parasitic extraction .. and then u can look for post layout simulation....
U may use the Start_XT(synopsys) of Dracula(cadence),They are the best tools for extract parameter on the layout.
Then, u may annotate the delay infor from the parameter into your netlist and run the layout-post simulation.
You have to annotate the extracted parasitics to your netlist and simulate it in the same testbench you simulated your RTL using a logic simulator (i.e. Modelsim, NCSim, VCS etc).
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