ADC and Memory design

Hello guys,

For my school project we are building a PC digital oscilloscope with a bandwidth of 10mhz and I need help with the design.

I want to sample a signal injected into a ADC and store the value in RAM. The thing is I don't want to lose any samples and you can't read and write to Ram at the same time(I don't think). Ok, so there are three channels (ch1,ch2,ext) but let's focus on one, since the design will be similar for the rest.

It consists of one ADC and two RAMs.

ADC will write to RAM1 until it's full then switch to Ram2, then I'll read from RAM1 then read from RAM2 when ADC has filled it.
Then this cycle continues. The data will then be read by a PIC micro controller and send to the usb port for processing.

I can program in C, assembly and VHDL. I'm so familiar with micro controllers and CPLDs. Any suggestions to better improve my current design?

Sounds like a good project!

Instead of using a regular RAM, consider a FIFO. It can write and read simultaneously, and it already contains the address counters. One popular FIFO manufacturer is Cypress.
https://www.cypress.com/

Thanks, I've never heard of FIFO before but sounds pretty cool. Read and write at the same time!!!!!! Simply amazing thanks again.

Good HDL-Projects at h**p://www.opencores.com

Cool, thanks I'll check it out. The site seems pretty cool.

Designing a 10Mhz analogic bandwidth DSO is not a simple thing even with FPGA.
An old and reference design could be found here:
https://alternatezone.com/electronics/dsoamk3.htm
Remember that 10Mhz analogic bandwidth means at least 20MHz Nyquist sampling, and an oversampling up to 40MHz will probably be necessary for aquiring all kind of shape signals.

success,

see this post
it will help you alot



and i would suggest to implement it on FPGA with internal RAM

regards,
Salma

salma ali bakr said:

see this post
it will help you alot

h**p://

and i would suggest to implement it on FPGA with internal RAM

regards,
Salma

Click to expand...

Yeah I guess your right about the sampling. I'm really not to strong on DSP. The thing that I'm having a problem with is the number of samples now. Using Nyquists theorm alittle more than two samples should be ok to reconstruct the signal in question on screen through software. We are thinking about setting the Fs(sampling rate) to 30mhz which causes some serious over sampling of lower frequency signals. Since the values for each channel is stored in ram(can't use fifo memory with current design). Right now we decided 2k of ram each channel no matter the frequency 0-10mhz. Is it ok to use 2K? I only have access to a CPLDs but FPGAs are faster and cooler.

I'll attach our power point presentation for the overall system design. This is our PDR that we presented. I'd appreciate your suggestions of the design.

Added after 2 minutes:

PowerPoint

well, there is no powerpoint at all

u should take in mind the access time of the RAM, in order to choose the size of it

Here it is. Sorry once again.