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Why I have If-then VHDL errors in my code?

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Opel_Corsa

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I am working on a CPU control unit, and my code is giving me ridiculous errors. Here's the part of the code in question (excluding the entity part):
Code: 
architecture behavioural of controlunit is
...
type mnemonic is (ADD, MOV, SUB, LOAD, MUL, ANDD, NEG);
signal m : mnemonic;
type state_type is (T1, T2, T3);
signal t : state_type;

-- Mnemonic definition
	with instruction_in(15 downto 11) select
		m <= ADD when "10001",
			 MOV when "11000",
			 SUB when "10010",
			 LOAD when "01000",
			 MUL when "10101",
			 ANDD when "10111",
			 NEG when "11010";
			
	  -- 3 State types
67	if (m = LOAD) then
68		t <= T1;
69	elsif (m = MOV or m = NEG) then
70		t <= T2;
71	else
72		t <= T3;
73	end if;
...
end behavioural;
The error messages are:
Error (10500): VHDL syntax error at controlunit.vhd(67) near text "if"; expecting "end", or "(", or an identifier ("if" is a reserved keyword), or a concurrent statement,
Error (10500): VHDL syntax error at controlunit.vhd(67) near text "then"; expecting "<="
Error (10500): VHDL syntax error at controlunit.vhd(69) near text "elsif"; expecting "end", or "(", or an identifier ("elsif" is a reserved keyword), or a concurrent statement,
Error (10500): VHDL syntax error at controlunit.vhd(69) near text "then"; expecting "<="
Error (10500): VHDL syntax error at controlunit.vhd(71) near text "else"; expecting "end", or "(", or an identifier ("else" is a reserved keyword), or a concurrent statement,
Error (10500): VHDL syntax error at controlunit.vhd(73) near text "if"; expecting ";", or an identifier ("if" is a reserved keyword), or "architecture"
Click to expand...

The reason why I can't see why it's giving these errors is that, my if-then statements are all correctly stated and I don't see anything wrong with them! Any help is greatly appreciated.

P.S> I'm not sure if using "if (m = LOAD)" would be a correct syntax. Is it?[/code]
 

vhdl else if

mmh, strange, I'll check that
 

if else in vhdl

first i think that you miss a "end if" in your code
you have two if so you mast write two end if
i wish to view all the code if you can
 

vhdl if statement outside process

U have write sequential statements inside the process.
The if else statements are sequential statements. so u need to write these statements inside the process.
I think u r trying to write state mechine it should be change the state with respect to clock,
include clock event statements in process sensitivity list, u can refer any VHDL state mechine examples.
 

vhdl if then else

if(m==load) is the correct syntax
if(condition)
u r using
if(assignment)
as girisha told make sure ur if part is in a process
 

vhdl illegal sequential statement

Hi,

There is missing a begin statement after the type and signal declarations.

Regards
 

error (10500) vhdl

Thanks very much for all the responses. First, the code that I posted was not a state machine. My code does deal with a state machine, but the one posted wasn't one. Also there are correct number of "end if" statements in my code. In any case, here's the full part of the architecture (the code is still incomplete, but I think it should compile nevertheless):

Code: 
architecture behavioural of controlunit is

type state is (READ1, READ2, S1, S2, S3, S4);
signal y : state;

signal instruction : std_logic_vector(15 downto 0);

type state_type is (T1, T2, T3);
signal t : state_type;

type mnemonic is (ADD, MOV, SUB, LOAD, MUL, ANDD, NEG);
signal m : mnemonic;

begin
	-- Mnemonic definition
	with instruction_in(15 downto 11) select
		m <= ADD when "10001",
			 MOV when "11000",
			 SUB when "10010",
			 LOAD when "01000",
			 MUL when "10101",
			 ANDD when "10111",
			 NEG when "11010";
			
	-- 3 State types
	if (m = LOAD) then
		t <= T1;
	elsif (m = MOV or m = NEG) then
		t <= T2;
	else
		t <= T3;
	end if;
	
	-- State Machine
	process(clk, reset)
	begin
	if (reset = '1') then
		instruction <= x"0000";
	elsif (clk'event and clk = '1') then
		case y is
			when READ1 => get_next_inst <= '0';
						  y <= READ2;
			when READ2 => y <= S1;
			when S1 => if (t = T1) then
						  datapath_in <= instruction_in(7 downto 0);
					   	  y <= READ1;
					   else y <= S2;
					   end if;
			when S2 => y <= S3;
			when S3 => if (t = T2) then
						  y <= READ1;
					   else y <= S4;
					   end if;
			when S4 => y <= READ1;
			when others => y <= READ1;
		end case;
	end if;
	end process;
	
end behavioural;
 

if else vhdl

Hi. The code:

Code: 
   -- 3 State types
   if (m = LOAD) then
      t <= T1;
   elsif (m = MOV or m = NEG) then
      t <= T2;
   else
      t <= T3;
   end if;

Is a sequential statement, not a concurrent one, and cannot be written outside a process begin/end block. Therefore, you can write it as:

Code: 
   -- 3 State types
   process(m) is
   begin
      if (m = LOAD) then
         t <= T1;
      elsif (m = MOV or m = NEG) then
         t <= T2;
      else
         t <= T3;
      end if;
   end process;

Or, you might use the concurrent assignment form:

Code: 
t <= T1 when m = LOAD else
       T2 when (m = MOV) or (m=NEG) else
       T3;

which can be safely written in an architecture body.

Hope this helps.
 

vhdl if condition

Thanks. Can you explain why you are considering m to be a clock? (since the if-then clause is sequential). I thought it was purely combinational...
 

syntax of if statement in vhdl

if is a sequential statement and it should be present in a process.
But when u synthesise if statements it becomes MUX which is combinational.
 

error (10500): vhdl

Hi.

In this process, m is not a clock. Synchronous (clocked) logic is described in a different manner in VHDL.

When you define a process:
Code: 
process(a,b,c) is
begin 
   if c = '0' then
      d <= a xor b;
   else
      d <= b xor c;
   end if;
end process;

The signals in the parentheses are the members of the process' sensitivity list. This means that the sequential statements in the process will re-execute and re-evaluate on any change of any signal in the list. The code described above is a purely combinatorial process:
The general rule is: when you describe complex combinatorial functions in VHDL, use processes and assign ALL inputs of the combinatorial process to the sensitivity list.

Synchronous processes (registers) need to trigger only on a rising or falling edge of a clock signal.

Code: 
process(clk,gsr) is
begin
if gsr = '1' then
   q <= '0';
elsif rising_edge(clk) then
   q <= d;
end if;
end process;

The process above describes a d type flip flop which samples the input d on the rising edge of clk. Note that only the global set-reset (gsr) and the clock signal are in the process sensitivity list. That's because these are the only signals the process must react to. As you can see, the presence of the clk signal in the sensitivity list is not sufficient to make it a clock signal. The condition that the change happens at rising_edge(clk) makes clk a clock signal, and the synthesis tools recognize clk as a clock signal through the rising edge condition.

The general rule would be: When describing synchronous logic, use processes triggered by a clk and an async reset signal (if needed), and make the assignment conditional by the rising_edge(clk) or falling_edge(clk). (see code above)

Also, don't mix sequential statements with sequential logic. VHDL as a language consists of sequential statements (which are executed in order) and concurrent statements (which are executed in parallel). Sequential statements do not directly correspond with sequential(synchronous) logic.

Hope this helps.
 

vhdl when else

The sequential statements should be included in a process statement. The IF Statements, Case Statements, Loop Statements, etc are all sequential processing and should be used inside a process. Am I right?
 

near process: expecting if

Thanks. But for a purely combinational process, even if you don't include the term process/end process; the code will be still synthesized as a purely combinational process by the compiler (in my case, Quartus II). At least that has been my understanding so far... I'd only use the process block when I was dealing with clocked systems with or without asynchronous reset.

Please correct me if I am wrong.
 

if condition in vhdl

Correct. You can describe combinatorial logic without using a process. But you cannot use if.. then.. else constructs outside of a process.

Writing the code
Code: 
   -- 3 State types
   if (m = LOAD) then
      t <= T1;
   elsif (m = MOV or m = NEG) then
      t <= T2;
   else
      t <= T3;
   end if;

is illegal outside of a process in VHDL.

To do this as a concurrent statement you need to use 'a<= x when y else z;' conditional assignment. Note that your degree of flexibility in describing the function is limited in comparison to using a process.

The paradigm of programming/designing in VHDL is to describe logic as concurrent processes. A process is a program element which executes sequentially in an infinitely small element of time ('delta' in the simulator). It does not have a specific intent for describing synchronous logic.

Every concurrent statement in VHDL is an implicit process. The assignment:
Code: 
a <= b xor c when z = '1' else '0';
is, internally in VHDL, the same as:
Code: 
process(b,c,z) is
begin
   if z = '1' then
       a <= b xor c;
   else
       a <= '0';
   end if;
end process;

We essentially use processes to describe a logic function, synchronous or combinatorial, by describing it through sequential statements (e.g. like programming in C). In that way we can achieve greater flexibility in describing complex logic through simple if-then-else rules, calculation through variables and functions, using cases and loops, rather than generating logic equations by ourselves. Describing logic functions through sequential statements is the main advantage of logic synthesis.

Imagine how would you do a combinatorial function which calculates the next state and outputs of a large state machine without using a process. Or, how would you write an arbitrary-length combinatorial decoder without generate statements.

When designing combinatorial logic, a general rule of thumb I follow is: use concurrent assignments for simple combinatorial logic, tristates and connections, and use processes for describing complex combinatorial logic such as state machine decoders.
 

    O

    Opel_Corsa

    Points: 2
    Helpful Answer Positive Rating
error 10500 vhdl

Understood. Thanks very much.
 

vhdl if outside process

You only show snipets of your code but I see one thing. Is the IF-THEN within a process? If not try somehting like this:

process (inputs for sensitivity list)
begin
if (something = some_value) then
out <= this;
else
out <= that;
end if;
end process;
 

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