How to simulate netlist with gated clock?

gated clocks

Hi all,

When I simulate netlist (Verilog style) with gated clock, I found the output is very different with what I see in RTL level (with a lot of red 'xxxx').

So I add tfile in NCSim to forbidden the delay and timing check in global scope (Because the design have no memory like RAM/FIFO).

The netlist waveform seems to be better, but there are also some trivial differences between RTL and netlist waveforms (e.g. some signal have one clock advance and some signal have one clock delay). I guess gated clock does not behavior like original clock and introduce race.

But how to understand gated clock simulation behavior? Any comments/reference will be appreciated!
Thanks!

Best regards,
Davy

gated clock

using "<=" in gated clock maybe help

gated clock verilog

I think the problem you saw might be caused by the initialization.
Be sure you set the initialization values for all signals in RTL leval.
Otherwise, after synthesis, in the gate-level simualtion, the timing
difference would cause unexpected values or unknown values.

gate level simulation with gated clock

Hi Davy!!
You can synthesize your behavior verilog whith option non modify clk .

gated clock netlist simulation

Hi
U done this after synthesis,
Reason 1:U may not initialized that gated clock enable signal or
2.There may be voilation (setup /hold)..

--satya

gate-level simulation gate clock

The most likely reason that you get 'strange' result when simulating a gate-netlist with gated clocks is that the different gated clocks are assigned at different delta-time, and thereby resulting in that the edge triggered registers are not evaluated/assigned at the exact same delta cycle.

A smal an simple example of problems with gate clocks in simulations (when not using any timing) is shown here:

In some simulators 'c' and 'b' may look as they are assigned the value from 'a' in the same clock cycle, the reason for this is that when 'clk' is changing (triggering a event) will make the 'b <= a' and 'gclk = clk & enable' assignment happen, then one delta cycle later the 'gclk' will trigger an event that makes the 'c <= b' assignment happen. So 'a' -> 'b' -> 'c' in the same clock cycle (but not in the same delta cycle).
If you add a small delay on 'b' and 'c', then it will work. But delays in RTL-code is ugly.
When running a gate-level simulation you should timing-data from your synthesis tool, then everything will 8hopefully) behave as it would in the real chip.

As usual I may have explained things in a more complicated way than necessary.

.net list initialization -c#

Thanks a lot!

I use DC to generate gated clock.
I heard latch is only used in gated clock in ASIC design. Is it right?

I think it must be gated clock cause the problem. I see the waveform.
And I found though data and clock change at the same time i.e at the
same delta time (I forbidden timing delay at global scope), clock
change is follow the data change.

As we all know data change must follow the clock change. So I guess
there must be gated clock cause some logic sequence chaos in
simulator.

Best regards,
Davy

verilog gated clock

Try clock gating in POWER COMPILER and ensure enable timing.

or check clock_gating_check in PT.

dc_shell clock gating

davyzhu said:

Thanks a lot!

I use DC to generate gated clock.
I heard latch is only used in gated clock in ASIC design. Is it right?

I think it must be gated clock cause the problem. I see the waveform.
And I found though data and clock change at the same time i.e at the
same delta time (I forbidden timing delay at global scope), clock
change is follow the data change.

As we all know data change must follow the clock change. So I guess
there must be gated clock cause some logic sequence chaos in
simulator.

Best regards,
Davy

Click to expand...

Hi !!!
I think what !
If You have uses only latch, you need set variable
hdlin_latch_always_async_set_reset = "true"

gated clock post simulation

Hi Shurik,

Can you tell me what tool do you use? Thanks!

Best regards,
Davy

synthesis gate clock

davyzhu said:

Hi Shurik,

Can you tell me what tool do you use? Thanks!

Best regards,
Davy

Click to expand...

Hello !!!
dc_shell or In GUI mode design_analyzer - $ynop$y$

synthesis gate clock simulation

hello davyzhu

can u please tell how to generate SDF file at pre layout level .. i read in ur message u r simulating the gate level net list with SDF ,, i am not sure of how to generate this file at synsthesis level ..
could u please tell me the command used for DC
suresh

clock gating netlist simulation

U have an initialization problem in ur netlist