Questions about Verilog code

Verilog Ques

1.Differentiate between Inter assignment Delay and Inertial Delay?
2.What is the difference between the following lines of code ?
reg1<= #10 reg2 ;
reg3 = # 10 reg4 ;
3.What is the difference between === and == ?

Re: Verilog Ques

a==b - a equal to b, result unknown if x or z in a or b
a===b - a equal to b, including x and z

always @(posedge clock)
a = b;
always @(posedge clock)
b = a;

There is a race condition when blocking statements are used.
Either a = b would be executed before b = a, or vice versa, depending on the simulator implementation. Thus, values of registers a and b will not be swapped. Instead, both registers will get the same value (previous value of a or b), based on the Verilog simulator implementation.

always @(posedge clock)
a <= b;
always @(posedge clock)
b <= a;

However, nonblocking statements used eliminate the race condition. At the positive edge of clock, the values of all right-hand-side variables are "read," and the right-hand-side expressions are evaluated and stored in temporary variables. During the write operation, the values stored in the temporary variables are assigned to the left-hand-side variables. Separating the read and write operations ensures that the values of registers a and b are swapped correctly, regardless of the order in which the write operations are performed.