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how to calculate the (W/L) of this current memory cell

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ballance

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w/l calculate

hello everyone
i want to simulate this circuit
but i don't know how to choice the aspect ratio and bias voltage

if -50uA < input current <50uA

please help me
thanks
 

that's design. first choose the currents (approximately) in each branch then choose the W/L to give the saturation voltage you desire.

Try 0.150v Vdsat for the mirrors, size M7/M8 to give the output current you need, and choose M2/M9 to set the class AB current in M7/M8 not too high.

PS - you don't bias using voltage, you bias using current mirrors. simplest way is to stack two diode-connected transistors and drive them with you desired bias current. these gates run the gates of M0/M1. I'm sure you know all this, but you can also make a high-swing cascode so the circuit runs at 2.5v.
 

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    ballance

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thank you for your help

but i still have some question

1. "choose the currents (approximately) in each branch" any magnitude is ok? or it has ratio between each branch?

2. "Try 0.150v Vdsat for the mirrors" what does the mirrors mean?

thanks
 

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