STOIKOV
Full Member level 4
hello! I designed a ring vco, simulated and did its layout. Then I simulate the extracted circuit (LEdit) and simulated again to obtain a frequency against control voltage curve. So the chip was fabricated and the experimental results show that the oscillation frequency is about 15 or 20% above the simulation frequency.
I hoped to obtain in lab a frequency below the simulated, maybe due to other parasitics not considered, but the frequency measured is larger.
Is this a normal behavior ? How can I justificate this percent of error. I was thinking on process variations, what do you think ?
I hoped to obtain in lab a frequency below the simulated, maybe due to other parasitics not considered, but the frequency measured is larger.
Is this a normal behavior ? How can I justificate this percent of error. I was thinking on process variations, what do you think ?