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the mechanism is that the up , and down pulse are narrow , so they can't turn on and of the charge pump switch , which will lead that there is not current from chareg pump will affect the loop filter
so the delay is added to rest path of the PFD to make these pulse more wide so they can turn on the switched , and the current pass through the Loop filter , so the loop detect this variations
the most simplest method to compensate for the dead zone is as follows:
find the critical path through your pfd , which is simply the worst case delay through your pfd across corners. Then put a series of inverters in the reset path so that the delay through these inverters is equal to the delay through the pfd.So in essence what this does is it makes your pdf output corrections pulses even when the pll is locked.So in effect your pll is a closed loop system even after it has locked, if dead zone is not compensated, the pll after it locks becomes an open loop system which cannot cutoff the VCO noise and hence causes timing jitter at the otuput. Hope its clear.
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