Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to make an LFSR with a loop length of 5 or 10 clock cycles?

Status
Not open for further replies.
E

Elephantus

Junior Member level 3
Junior Member level 3
Joined
Jul 11, 2005
Messages
31
Helped
4
Reputation
8
Reaction score
0
Trophy points
1,286
Activity points
1,627
Hi.

Does anyone know the taps to make an LFSR with a loop length of 5 or 10 clock cycles?

Thanks in advance.
 

Re: LFSR design question

Xilnx has a application note regarding LFSRs (XAPP210). The last section has all the taps for a 3 to 168 clock cycle LFSR. See hxxp://www.xilinx.com/bvdocs/appnotes/xapp210.pdf
 

    E

    Elephantus

    Points: 2
    Helpful Answer Positive Rating
LFSR design question

LFSR is used in crc computation. so, i guess this should be of some use for u.

**broken link removed**
 

LFSR design question

For Loop Length of 5 take 3 DFF & when value 110 cames it should be connected 2 nand gate through clear of DFF
Thanks
Anmol
 

Re: LFSR design question

just if you have the book

HDL chip design by Douglas Smith.....go through that once

there is a detailed explanation abt LFSR

good luck
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top