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A basic question on the FIR design in FPGA

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eruisi

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I need to design a low-pass digital FIR in FPGA. Can you guys give me some hints how to optimize it? The cut-off frequency of FIR is 5MHz. The platform I am using is Altera Quartus 4.

First optimization is for area.
I'm using 64-tap architecture. After all kinds of optimizations that I can come up with (symmetry makes coefficients to half, some coeffecicents are taken out (0,1)or replaced by shifters (+/-2, +/-4, +/-8, ...). Still it's huge. A lot of area is taken by the multipliers.

Second one is for speed. How to pipeline the final adding of all results from 64 taps? Is there any tools can do it automatically?

Last one is for power, of course simplifying hardware can reduce the power. Any other techniques can be applied here without huge impact on performance?

I really appreciate your help!
 

What is your target device? What is the signal's sample rate and bit width?
If you can clock your multiplier-accumulators (MACs) at 200 MHz, for example, then you won't need very many of them.
If your device doesn't have built-in multipliers, then consider a better device.
 

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    eruisi

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Thanks.

Data bit width is 16
Target device is Starix EP1S40B956C5
Data rate is only 20MHz or so

What are the typical techniques to decide the order and coefficients of an FIR design?

In architectural aspect, using more hardware but working at low frequency, or using less hardware (time multiplexing) but working at higher frequency, general speaking, which one is better in term of power consumption?

I found that when I simplified the hardware, reduced the area, the dynamic power is reduced, but the static power remains, which means the unused hardware in the chip still consumes power as usual. Then how to reduce the power consumption of unused hardware in the FPGA chip?

Thanks again!
 

I've never used Altera FPGAs, but I think that device has 54 18-bit MACs that can go 278 MHz. I don't know how easy/difficult it is to achieve maximum speed in Altera parts, but I would try using 6 MACs running at 220 MHz, with each one processing 11 filter taps.

In general, for good FPGA resource utilization, you should run the clock fast, use lots of pipelining, and do things sequentially to keep most of your logic busy on every clock cycle.

I use MATLAB to create digital filter coefficients. It makes the job pretty easy. MATLAB can also spit out VHDL or Verilog code, but I prefer writing my own HDL.

I don't know details of Stratix power management. In Xilinx FPGAs, static power is usually small compared to dynamic power.
 

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    eruisi

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eruisi said:
Thanks.


I found that when I simplified the hardware, reduced the area, the dynamic power is reduced, but the static power remains, which means the unused hardware in the chip still consumes power as usual. Then how to reduce the power consumption of unused hardware in the FPGA chip?

Thanks again!
Click to expand...


I've asked at Altera for a similar problem. There is nothing to do.
How much is your current drawn by the VCCIO, VCCINT and VCCPLL in static condition and which is when runnig (I presume VCPLL and VCCO are almost the same)?

thx,
 

    E

    eruisi

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I've never used Altera's FPGAs but as I know there is a slice called DSP48 in xilinx's ones which includes some pipline registers.
using them a higher speed (in Virtex 4 up to 500 MHZ) is achievable .you can put them befor the multiplier block or between MUL and ADD blocks and also in the output. by casscading 64 DSP48 slices and (there are 512 dsp48 blocks in Virtex 4 sx55) , you'll have a result at every clock cycle.
these blocks can be programmed by Xilinx System Generator in xilinx devices and by DSPbuilder in Altera's.
Have a nice time
 

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    eruisi

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Thank you guys for the kindly reply. This community is great!

I have another general question: Besed on the requirement, I need to focus more on power efficiency than area/speed. I understand that I can do nothing for static power since the target device has no clock gating etc.

For dynamic power: what are techniques for low power in general for FPGAs, like pipelining or anything else?
 

You didn't answered to my question, please.
 

If sampling frequency 20MHz, and cutoff frequency 5MHz, possible using half-band filter. Impulse responce of this filter symmetrical, and even coefficients is zero (except central tap).
 

Optimization Techniques for Efficient Implementation of DSP in FPGAs
 

use matlab 7 . it will also generate its verilog or VHDl code
 

You can go to Xilinx website. It has nice filter implementation examples.
 

Sorry I didn't pay attention to your question.
Where can I get thouse results?

melc said:
You didn't answered to my question, please.
Click to expand...
 

Yes, Matlab is good tool for design FIR and also IIR.

The second think is you should have ability to handle Fixed point number operation.

Then you can design any filter.
 

Hi,

Tyder who produce ONEoverT Digital Filter Designer will create filter and other IP for you for $50 via Paypal. Design your filter using the demo version of ONEoverT or Tyd-IP Code Generator, save the project file (*.fil) and send it to them. You need to specify what device you want to target. They will send you back the edif files or .ngc. You can then use this in your FPGA.

Bob
 

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