Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Help me build a coffee maker using VHDL

Status
Not open for further replies.

lanun_kampung

Newbie level 4
Newbie level 4
Joined
Oct 21, 2006
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,343
i need to build a coffee maker using verilog HDL.start from water boiling- mixing -stir -brew...any1 can help.???
 

coffee maker problem

Some of us don't know how to make coffee. ;) Are you building real hardware, or just a simulation? The first step is to carefully describe the controller's various input/output signals, and the required sequence of actions. Then you can design a timer that triggers the various control signals at the required times. What parts have you completed so far?
 
coffee maker problem

hm...simulation is ok.have just completed the timer and converted it to 7-segment display.but still researching the code for the whole process.

act,i'm a student.2nd year electronic & electrical engine. at UTP...your help is appreciated
 

Re: coffee maker problem

for stiring use timed ultrasonics piezo transducer

for mixing some sort of plastic unit with feeder tubes and release of a chamber that fills for say one spoon coffee and by up to 3 sugar chambers that can release

you using instant coffee??? or ground ???
water spashback is an issue so some sort of protected removable unit as a guide to keep some distance between the coffee sugar and water etc
for hot water its best to use a shower and hack it for parts
you can keep it ticking over using a thermister etc to control it then ramp up the power just before release time to get the level right
you could use a measuing device to guage the depth of the water in the cup
laser or sonic or prob is ir is no good

make a flow chart on a white board and this way you can adjust it easily


its a fun project

and good luck:D
 
coffee maker problem

tq guys...hmm..but 1st i have to show it into verilog file.
 

coffee maker problem

tq to all who help me...
this is my program. i'm using quartusII.

//timer
module clock_div (Q0,CLK,coffeetype);
input CLK;
input coffeetype;
output Q0;
reg CLKdiv;
reg [23:0] i;
initial
begin
i=0; CLKdiv=1'b0;
end

always @ (negedge CLK)
begin
if(coffeetype)
begin
if (i<24'b111111111111111111111111) i=i+1;
else begin
i=0; CLKdiv=~CLKdiv;
end
end

else
begin
if (i<24'b110000000001000111101100) i=i+1;
else begin
i=0; CLKdiv=~CLKdiv;
end
end

end
assign Q0=CLKdiv;
endmodule

//water sensor
module water_sensor (waterstatus,warninglight,CLK, waterlevel);
input waterlevel,CLK;
output waterstatus,warninglight;
reg waterstatus,warninglight;
always@(posedge CLK)
if (waterlevel==1)
waterstatus =1'b1; //boilerNotEmpty
else
waterstatus =1'b0;//boilerEmpty
always@(posedge CLK)
if (waterlevel==1)
warninglight = 1'b0;
else
warninglight = 1'b1;
endmodule

//warmerplate sensor and valve pressure
module plate_sensorAndvalve_pressure (openclose,platestatus,CLK, pot);
input pot, CLK;
output openclose,platestatus;
reg openclose,platestatus;
always@(posedge CLK)
if (pot==0)
platestatus = 1'b0; //turns off plate warmer
else
platestatus = 1'b1; //restart plate warmer
always@(posedge CLK)
if (pot==0)
openclose = 1'b1; //open valve to stop water flow
else
openclose = 1'b0; //close valve to start water flow
endmodule

//mixture sensor
module mix_sensor (mixstatus,warninglight1,mixsense);
input mixsense;
output mixstatus,warninglight1;
reg mixstatus,warninglight1;
always @ (mixsense)
case(mixsense)
1'b0 : mixstatus = 1'b0; // indicate that there are no mixture in the container
1'b1 : mixstatus = 1'b1; // indicate that there are mixture in the container
endcase
always @ (mixsense)
case(mixsense)
1'b0 : warninglight1 = 1'b1; // turn on mixture-warning light for error
1'b1 : warninglight1 = 1'b0; // mixture-warning light is off if there are mixture in container
endcase
endmodule

//main coffee maker program
module coffee_maker(dispenserfilter,Q0,boiler,warmerplate,timer,mixcontainer,mixstatus,warninglight1,waterstatus,platestatus,valve,Button,Setclock,CLK,pot,waterlevel,warninglight,mixsense,coffeetype);
input Button,Setclock,CLK,pot,waterlevel,mixsense,coffeetype;
output dispenserfilter,Q0,boiler,warmerplate,mixcontainer,waterstatus,platestatus,valve,warninglight,mixstatus,warninglight1;
output [4:0]timer;
wire START;
reg [4:0] timer;
reg mixdispenser,boiltimer,timingprocess;
assign START = (Button||Setclock)&& timingprocess;

//instantiate water sensor
water_sensor WS(waterstatus,warninglight,CLK, waterlevel);

//instantiate plate sensor and valve pressure
plate_sensorAndvalve_pressure PSVP(valve,platestatus,CLK, pot);

//instantiate mixture sensor
mix_sensor MS (mixstatus,warninglight1,mixsense);

assign boiler = START && waterstatus && mixstatus && boiltimer ; // to make boiler heater turn on or off
assign #(100) warmerplate = START && platestatus && mixstatus ; // to make plate heater turn on or off
assign #(200) mixcontainer = boiler && warmerplate ; // to make mixute container open or close
assign dispenserfilter = START && mixdispenser;
//instantiate timer
clock_div CD(Q0,CLK, coffeetype);

always@(posedge Q0)
begin
timer=timer+4'b0001;
end

always @(timer)
begin

case(timer)
4'b0101: begin mixdispenser=1'b1; end
4'b0110: begin mixdispenser=1'b1; end
4'b0111: begin mixdispenser=1'b1; end
default: begin mixdispenser=1'b0;end
endcase
end

always @(timer)
begin

case(timer)
4'b0000: begin boiltimer=1'b1; end
4'b0001: begin boiltimer=1'b1; end
4'b0010: begin boiltimer=1'b1; end
4'b0011: begin boiltimer=1'b1; end
4'b0100: begin boiltimer=1'b1; end
4'b0101: begin boiltimer=1'b1; end
4'b0110: begin boiltimer=1'b1; end
4'b0111: begin boiltimer=1'b1; end
4'b1000: begin boiltimer=1'b1; end
4'b1001: begin boiltimer=1'b1; end
4'b1010: begin boiltimer=1'b1; end
4'b1011: begin boiltimer=1'b1; end
default: begin boiltimer=1'b0;end
endcase
end
always @(timer)
begin

case(timer)
4'b0000: begin timingprocess=1'b1; end
4'b0001: begin timingprocess=1'b1; end
4'b0010: begin timingprocess=1'b1; end
4'b0011: begin timingprocess=1'b1; end
4'b0100: begin timingprocess=1'b1; end
4'b0101: begin timingprocess=1'b1; end
4'b0110: begin timingprocess=1'b1; end
4'b0111: begin timingprocess=1'b1; end
4'b1000: begin timingprocess=1'b1; end
4'b1001: begin timingprocess=1'b1; end
4'b1010: begin timingprocess=1'b1; end
4'b1011: begin timingprocess=1'b1; end
default: begin timingprocess=1'b0;end
endcase
end
endmodule
 

Re: coffee maker problem

In the last two case conditions, why don't you inverse the default condition with others? In that case you should write 4 conditions + 1 default condition, instead of 12 conditions + 1 default condition! The RTL code would be "full" the same.

Nicola
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top