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default binding problem in gate-level simulation

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guiliu

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I got compiling warning message from Modelsim: " No default binding for component 'xxxxx'. (No entity named 'xxxxx' was found.) " from gate-level simulation.

The "xxxxx" stands for the gate name. The gate-level netlist is generated from Design_analyzer.

I used the same testbench as used in RTL simulation.

How to solve this problem?

Many thanks!
 

you need to include your simulation library in your gate netlist
 

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    guiliu

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U have to include u r verilog (or vhdl) library file which describes the standard cell functionality and timing into u r simulation environment.

Regards,
dcreddy
 

Thank you all!

I have tried to include the GTECH library into my GTECH netlish for gate-level simulation ( I do not have other technology libraries available in Modelsim), and the warnings are gone.

But for big designs, this method seem to be tedious. So I'd like to try to include the library to the simulation environment (ModelSim), like dcreddy said. But I have 2 questions:

1. How to import the umc library to Modelsim?
2. if the library is imported, how can i set it to simulation environment?

Thanks a lot !
 

Hi
If u r using vhdl or verilog there exists a techfile .v or .vhd(in 90 nm CMOS u have corelib.v). u just compile this with ur source code netlist and simulate.

cheers
srinivas
 

hi,
first ,modlesim is very slow for gate level sim, so if possible you can try vcs/ncsim. they are faster than modelsim.
second, using command line to compile library.v , it's easy
 

Thank u all for ur reply!

What can i do if the library is in db format?
 

U should include your simulation model of the std cell you uesed.
 

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