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Synopsys's VMM and Mentor's AVM

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davyzhu

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Hi all,

I want to use SystemVerilog to construct next generation of my testbench.

And I found Synopsys provide VMM while Mentor provide AVM. Anyone can give some comment on these two methodology? Or are they similar?

I don't know if Synopsys's VMM is open document and open source code.

The AVM cookbook/source code, you can download a free copy from:
https://www.mentor.com/products/fv/_3b715c/cb_dll.cfm

Best regards,
Davy
 

VMM is more like system verilog reference manual, it talks about the coding guidelines, recommendations & rules.
AVM is about verification methodology which you can use for any language.
 

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    davyzhu

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VMM and AVM are both class bases verification methodologies... VMM is not open source, but AVM is open source !!! AVM makes use of TLM concepts for communication between testbench blocks while VMM makes use of much raw mailboxes and stuff... But, both have there pros and cons !!!
You can also try out OVM which is URM + AVM, much more interesting stuff !!!! :D
OVM is open source...
 

Hi,

vizpal said:
VMM and AVM are both class bases verification methodologies... VMM is not open source, but AVM is open source !!! AVM makes use of TLM concepts for communication between testbench blocks while VMM makes use of much raw mailboxes and stuff...
Click to expand...

Not true - VMM uses channels - very similar to tlm_fifo of AVM. It has built-in callbacks too - lot more powerful than plain mailbox.


You can also try out OVM which is URM + AVM, much more interesting stuff !!!! :D
OVM is open source...
Click to expand...

I recommend OVM than AVM if starting new. But remember OVM/AVM/uRM is new and immature against VMM. VMM is open source for any "real user" - as you can get the source code for your use!

Ajeetha, CVC
www.noveldv.com
 

I think that AVM is better one.
 

I think,it depend on your tool which you will use,
 

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