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How to test my ESD layout ?

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sophiefans

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The design rule says that the circuit will could stand with 2KV HBM if i do my layout all by the rules. But, how could i test my esd layout which has been made by design rule?


thanks
sincerely,
sophiefans
 

Re: ESD thing

No doubt, how well ESD can be avoided is depends on the protection circuits. However, layout play important role also.

What i normally do is to minimize ESD path resistance to < 0.5Ohm at any possible cases, by using wide metal and stacked metal. You can use a typical HBM model to simulate the ESD circuit + manually add some reasonable metal resistance based on your final layout. This could better tells how well your ESD protection is before tapeout.

Pls tell me if there is any other clever method using Cadence. Thanks.
 

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    sophiefans

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Re: ESD thing

sengyee88 said:
No doubt, how well ESD can be avoided is depends on the protection circuits. However, layout play important role also.

What i normally do is to minimize ESD path resistance to < 0.5Ohm at any possible cases, by using wide metal and stacked metal. You can use a typical HBM model to simulate the ESD circuit + manually add some reasonable metal resistance based on your final layout. This could better tells how well your ESD protection is before tapeout.

Pls tell me if there is any other clever method using Cadence. Thanks.
Click to expand...

Thanks for your reply. I am a fresh man in this field and don't have much experience. So i am sorry and i hope we can share experience some times later.
 

Re: ESD thing

Hi,

I am not sure why u need to say sorry. Perhaps, it could be my lousy english that make you feel unconfortable. If this is the case, I apologize.
I would like to clarify that I am here to share and learn, not criticize. :D
 

Re: ESD thing

Maybe we all made mistakes. That was not my real intention too.

For my esd layout, i can't extract out mos at all if the SAB layer is inserted.
 

ESD thing

There two kind of ESD protection devices: breakdown (TFO,GGNMOS,GCNMOS,SCR and others) and non-breakdown (diode, mosfet, bip. circuits and clamps).
Breakdown devices is requred the situable/proper models for simulation. Usually fabs doesn't provide such models or such devices for ESD protection at all. Non-breakdown devices allow simulation.
If ESD protection strategy provided by ur fab use non-breakdown device u can simulate it (but u must include parasitics lumped element of layout and package of course). But i think it'll be difficult to u. It's better for u to take great care with layout design and follow fab layout rules. In this case u'll have ur 2kV of ESD protection :).
For more details about ESD protection i can refer u to good book
 

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    sophiefans

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ESD thing

i agree DenisMark.
BD is difficult to simulate using spice, maybe some special software can help you. the performance of BD devices is affected by process and other parameters, NBD behave more like a circuit.
 

Re: ESD thing

I have finished my esd layout by nmos according to design rule. But i don't know if it could rely on it without simulation. I want to try if someone can explain it more clearly. I found some chip use nmos only for esd in practice. I mean if i could use nmos only like them or should use another pmos for low voltage.


Thanks for your reply above.
sincerely,
sophiefans
 

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