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[ncsim] stop -> force -> run error?

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davyzhu

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ncsim force

Hi all,

I want to write a Tcl in ncsim to do below work.
1. stop when $signal is 1
2. set the lock to force stop only stop once
3. force $other_signal
4. continue run
5. force $other_signal back
6 continue run

But ncsim said "cannot run command executed from a stop -execute script".

Any suggestions, thanks!

Code: 
#----- Tcl begin ---
set lock 0
stop -silent -name stop_name -cont -cond { [value $CLK] == 1 && $signal ==1 && $lock == 0} -exec {
    set lock 1
    force other_signal = 8'b10010000
    run 50us
    force other_signal = 8'b10001010
}
run 50us
#----- Tcl end ---
Best regards,
Davy
 

forces in ncsim.log

Is it for simulation of verilog code?
 

force ncsim

Hi,
Not sure if stop inside a stop is allowed, if so the following should work:

Code: 
#----- Tcl begin ---
set lock 0
stop -silent -name stop_name -cont -cond { [value $CLK] == 1 && $signal ==1 && $lock == 0} -exec {
    set lock 1
    force other_signal = 8'b10010000
    stop -time -relative 50 us -cont -exec {  force other_signal = 8'b10001010}
}
run 50us
#----- Tcl end ---

If this doesn't work let me know, we can find some thing else.

Regards
Ajeetha, CVC
Contemporary Verification Consultants Pvt Ltd. http://www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 http://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar
 

    D

    davyzhu

    Points: 2
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ncsim stop simulation

Hi aji_vlsi,

Thanks a lot, and I will try your method next week :)

Hi Shurik,

Yes, it's Verilog simulation.

Best regards,
Davy
 

force ncsim

Hi davyzhu!

I am not using the Tcl script for simulation.
I write testbench which control the simulation.

Best regards.
 

force value ncsim

Hi ,

If possible try to do the same in testbench ( if you have visibility of the signal ...) .
This will increase perfomance than using Tcl .


Thanks & Regards
yln
 

    D

    davyzhu

    Points: 2
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ncsim assertions

yln2k2 said:
Hi ,

If possible try to do the same in testbench ( if you have visibility of the signal ...) .
This will increase perfomance than using Tcl .


Thanks & Regards
yln
Click to expand...
Good point. Given that it is Verilog, visibility is not an issue at all. EVen if you were using VHDL, one can use signal_spy/nc_mirror/hdl_xmr feature to achieve the same.

Ajeetha, CVC
www.noveldv.com
Contemporary Verification Consultants Pvt Ltd. http://www.noveldv.com
* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5 http://www.systemverilog.us/
* SystemVerilog Assertions Handbook
* Using PSL/Sugar
 

    D

    davyzhu

    Points: 2
    Helpful Answer Positive Rating
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