what is wrong with my PLL loop filter voltage?

Hello everyone,

I run a transient on my PLL to see the locking process. But after long simulation (30us) with loop bandwidth about 200khz. The loop filter voltage seems not settled which is not as flat as I expected but with ripples and some unstabled DC component.

The loop filter is a regular third order and the loop filter voltage is connnected to the tank capacitor(gate of a varactor) of a LC cross-coupled VCO.

Please see the attached transient and give me some insights on what is possibly wrong. There is ripple in the loop filter voltage the ripple is 4mv peak to peak. And the ripple is about 3GHz which is exactly two times of the VCO oscillation frequency.


Thanks.

How about your charge pump? Does the Nmos current match well wtih PMOS current

That is very simple! It is the rectified coupling of the varactor cap to the PLL loop filter cap. I assume that you using a differential tank circuit with a differential varactor. Because the varactor is nonlinear and the tank voltage have second order harmonics on the single ended voltage you see the second harmonic current at the varactor input. That lead to a small voltage drop across the loop filter cap.

Hi rfsystem,

My first guess is also this coupling and you make it clear. My thinking is that since the ripple is high frequency so it may not cause serious problem to meet the blocker specification for the receiver. The PLL is used to generate LO signal for a mixer in a RF receiver.

What I am worrying about is that the DC shift possibly caused by the ripple(the ripple's DC average is not zero). This DC shift will make the loop filter voltage not flat even in the locked state as shown in the figure. And that will lead to frequency shift of the PLL and may cause trouble for digital demodulator after the mixer and base band ADC.

Is there anyway to decrease this DC shift?

Thanks.

Your are right, the possible DC effect of the ripple is about 400-500uV. If you havin about 100MHz/V for a combined digital/analog control you get 40-50kHz shift. So there is a small amplitude to frequency shift. I think that is no issue unless the amplitude of the VCO is not impacted by something else.

Thanks rfsystem,

The differential vco output amplitude is 100mv lower than vdd and the Kvco is about 30MHz/v. so it seems 15kHz offset is there for my PLL.

But why do you think 40 to 50KHz offset is ok? I am not familiar with digital specifications.

eejli said:

But why do you think 40 to 50KHz offset is ok? I am not familiar with digital specifications.

Click to expand...

Hi.

That realy depends. There's always a trade off: locking time vs. Δf (in your case Δf is 40-50kHz). You can redesign your loop filter (decrease loop bandwidth) which will result in ripple decrease, but at the same time it will increase locking time. If you have a specification for your pll regarding locking time try to come as close as you can (with a margin for worst case phase shift between reference and divided VCO signals). Then measure ripple amplitude. If that is still too much then you can also try redesigning charge pump and loop filter to decrease leakage current or you can try to decrease phase/frequency detector dead zone. But that's mostly cosmetics - focus on loop filter first.

Best wishes and good luck.

I think it is ok because this frequency shift will be compensated by the PLL loop. So there is only a small change of the VCO voltage. For the LO performance typical phase accuarcy over time is important, which is called phase noise or integrated EVM.

I think the ripple is ok.

thanks guys,

I have to return to this topic since in the lab I measured the PLL frequency and find the output frequency is almost exatly the frequency that it should be(reference frequency times divider ratio) within the reference crystal ppm range.

But a weird thing is that I need to offset the fractional part of the divider ratio to get the baseband demodulator ouput a better video signal.

Our digital designer says I need to take more look on the PLL design especailly the dividers following the PLL(those divider is out of the PLL loop which is uded to divide the PLL output further down to match the RF signal frquency). I donot know whether he is right. will those dividers change the PLL output frequency? I doubt it is true.

Is there any possible other reasons that can explain this frequency offset problem? Will the loop filter ripple cause the frequency offset?

Thanks.









. It seems I need to manually offset the simga delta division ratio a little bit to make the demodulator in the baseband to have a good output video.

Hi eejli,

What do you mean by frequency offset?

Does it mean that when you set the modulus to be 70.5 but the actual
modulus becomes 71.5?

If so, this may be a problem of the DSM.

e off: locking time vs. Δf (in your case Δf is 40-50kHz). You can redesign your loop filter (decrease

Arein,

Let us give an example.Say the ideal division ratio is 40.5 the PLL output frequency is exactly 40.5*Fref(27MHz)+50kHz, I suppose this 50kHz is from crystal ppm accuracy(like 100ppm-->2.7KHz*40=108kHZ>50kHz).

But I need to adjust the sigma delta division from 0.5 to 0.5001 to get our base band demodulator output a good quality video. A direct explaination is that the PLL output has some frequency offset. Somebody tells me that I cannot trust a 2GHz signal from a spectrum analizer since it is high frequency.
Is he right?

in my pll,i also see the phenomena.it is caused by the 2nd order harmonics in the output of the vco because they have the same phase.right?and then,how to understand they have the same phase?