How to solve the unmapped key points problem?

Hi all,

When I perform the lec using the cadence tools CONFORMAL, There's too much of umapped key points in my design. This bring to the huge number of unequivalent when i do the comparison between the revise and golden of my rtl and gate.
1. What's is the unmapped key point? What cause the unmapped key points ? Example?
2. How to solve this unmapped key points problems ?


Thanks...

Re: Unmapped Key Points

Hello,

try to:
check constraints, check libraries check options, maybe you might need some renaming rules, generate reports to get some info from there.

Hope this helps a little bit!

Re: Unmapped Key Points

HI,
you should clear the un-mapped points before comparison. Start based on categories like Not-mapped, Unreachable & Extra.
If you are doing formal check between RTL and Netlist, there is possiblity that synthesis tool has optimized some signals in RTL and removed unused signals. IN this case if LEC is unable to understand the logic, you may get un-mapped points.
Another case is when you insert DFT logic on synthesis netlist (scan insertion etc), you may get some extra ports or signals used for DFT.
Go through the list of un-mapped points. Discuss them with concern RTL designer.
Un-mapped points are OK unless synthesis tool has done some un-wanted optimisation.

Hope this will help you.
jitendra

Re: Unmapped Key Points

Hi,
Thanks for your info. The unmapped is caused by unreachable!

The unmapped report is something like this
Unmapped point (unreachable : all path to output is blocked)

How should I solve the problem ? THanks

Unmapped Key Points

if the point is unreachable, we don't care about it

Re: Unmapped Key Points

Hi,
Unreachable points should not be a major issue.
Use following command for mapping method
set mapping method -name first -unreach
This will increase your run time. but it will map unreachable points as you are adding switch -unreach.

Regards,
Jitendra

Re: Unmapped Key Points

still there's a lots of unequivalent.
I actually doing the lec on rtl2rtl

This are the un-equivalent occurred although I confirm I nv done any chances on this files...
Can some1 tell me what's the message is trying to tell me ?
I am freshgrad.... No mentor here....zzz

Diagnosis points: [INPUT]
(G) + 149244 BUF /U_core/U_sleep_block/U_ram_n_10k/u_ram_10kx8/addr[0]
(R) + 149531 BUF /U_core/U_sleep_block/U_ram_n_10k/u_ram_10kx8/addr[0]

There are extra but mapped key points in this logic cone
================================================================================
ID Type Name
--------------------------------------------------------------------------------
(R) + 402 'DFF' /U_core/U_core_8051/u_R80515/U_CPU/nr_cycles_reg_3
(R) + 406 'DFF' /U_core/U_core_8051/u_R80515/U_CPU/curcycle_reg_3
================================================================================


Non-equivalent signal and its error candidates
================================================================================
ID (R) Type Likelihood Name
--------------------------------------------------------------------------------
149531 JAALAA_SRAM_10240x8:'PIN' /U_core/U_sleep_block/U_ram_n_10k/u_ram_10kx8/addr[0]
------- Candidates -------------------------------------------------------------
1: 406 'DFF' 1.00 /U_core/U_core_8051/u_R80515/U_CPU/curcycle_reg_3
2: 28593 'AND' 1.00 /U_core/U_core_8051/u_R80515/U_CPU/U$324
3: 28613 VDW_LT_s5_CIM 1.00 /U_core/U_core_8051/u_R80515/U_CPU/lt_281
4: 29099 'AND' 1.00 /U_core/U_cpu_bus_bridge/U$98
5: 29105 'AND' 1.00 /U_core/U_cpu_bus_bridge/U$95
6: 29111 'OR' 1.00 /U_core/U_cpu_bus_bridge/U$223
7: 29122 'INV' 1.00 /U_core/U_ram_arbiter/U$89
8: 52983 VDW_WMUX16_CIM 1.00 /U_core/U_cpu_bus_bridge/U$167
9: 28558 'NOR' 0.87 /U_core/U_core_8051/u_R80515/U_ALU/U$898
10: 28560 'NOR' 0.87 /U_core/U_core_8051/u_R80515/U_ALU/U$894
================================================================================