in a CMOS circuit, what is meant by drive strength ?

in a CMOS circuit, what is meant by drive strength ? For example in TSMC cell library there are cells labeled AOI221X1 AOI221X2 etc. What is the significance of X1, X2 etc. Kindly give me a detailed reply by stating the defenition of drive strenth, signaifcance and factors affecting drive strenth.


With thanks

drive strength capacitance

Hi,
In CMOS circuits the drive strength is the Current Capability of the device i.e. Ids.

Ids can be increased by incresing the W/L ratio.

It is with this current the present state can drive the next stage i.e. charge the next stage capacitance.

Thanks
Shaikh Sarfraz

drive strength rise time

if you check the speed of each cell you will see thath going from 1 and further the cell are quicker but also consume more power and area.

cmos inverter drive strength

X1 means only one transistor(include a pmos and a nmos) in cells's drive stage.

X2 means two transistor in parallel in cells's drive stage..

x4 means four transistor in parallel in cells's drive stage.

more transistor, more current drive ability.

best regards

beejan said:

in a CMOS circuit, what is meant by drive strength ? For example in TSMC cell library there are cells labeled AOI221X1 AOI221X2 etc. What is the significance of X1, X2 etc. Kindly give me a detailed reply by stating the defenition of drive strenth, signaifcance and factors affecting drive strenth.


With thanks

Click to expand...

drive strength 2x

General it specifies the driving strength

xL--> 0.5xdriving strength of cell (low-drive cell)
x1--> 1x driving strength cell
x2--> 2x driving strength cell
etc...

You can also read in databook of standard cell library

gate drive strength

The symbols, 1X, 2X, 3X...etc in an ASIC flow in used for convinience. What it means is a gate with 2X drive strength will have the same rise/fall time while driving a capacitance of 2C farads as that of a gate with X drive strength driving a capacitance of C farads. You can look at the schematic and see that gates with 2X drive strengths have approximately twice the widths on output pull up/pull down trasistors as comapred to the same gate with 1X drive strength. Similarly definitions for 3X, 4X etc.

This is to ensure that ratio of width to load capacitance remains constant, thus resulting in the same transition times. It is desired that the transition times in an ASIC chip be within a certain limit (DRV critereon). This will be met if the following rule is followed -

If 1X drive strength is sufficient to drive a load of C farads (ie, transition time is satisfactory) then 2X drive is satisfactory to drive loads between C farads and 2C farads, 3X drive is sufficient to drive loads between 2C and 3C farads....etc.

Hope this helps.

drive strength of cell cmos

drive strength is defined interms of basic gate i.e. NAND / NOT gate
let the basic gate is NOT
then X2 defines the gate you are using can drive cap ie is 2 times of NOT gate
generally NOT gate is used for define metrics in CMOS technology

Re: drive strength of cell cmos

shaikhsarfraz said:

Hi,

Ids can be increased by incresing the W/L ratio.

Click to expand...

funster said:

X2 means two transistor in parallel in cells's drive stage..

x4 means four transistor in parallel in cells's drive stage.

Click to expand...

the quotes aboves suggest two different approaches to increase the W/L. Individually increase the transistor's W/L or put in more transistors.

What do vendors normally do?

Re: drive strength of cell cmos

vijay82 said:

the quotes aboves suggest two different approaches to increase the W/L. Individually increase the transistor's W/L or put in more transistors.

What do vendors normally do?

Click to expand...

They don't want too tall transistors because the height of transistors determines the cell row height so that all the cell must have the same height, which may waste a lot of spaces in low power/low drive cells.
Coupling multiple transistors is more flexible to have well balanced cell collection.

Re: drive strength of cell cmos

lostinxlation said:

They don't want too tall transistors because the height of transistors determines the cell row height so that all the cell must have the same height, which may waste a lot of spaces in low power/low drive cells.
Coupling multiple transistors is more flexible to have well balanced cell collection.

Click to expand...

I'm sorry I didn't understand clearly. What you're saying is multiple transistors are packed more compactly than individual tall transistors and thus the cell height is reduced?

Re: drive strength of cell cmos

vijay82 said:

I'm sorry I didn't understand clearly. What you're saying is multiple transistors are packed more compactly than individual tall transistors and thus the cell height is reduced?

Click to expand...

To increase the W on individual transistors, you have to have large(tall) diffusion area, which essentially makes the cell height tall.
Now consider to design a new cell with low drive strength(smaller W). This new cell has to have the same height as others, but you don't want to have a large diffusion area to achieve the shorter W. You need to put a small diffusion in a large(tall) cell foot print, which means there are a lot of open spaces within a cell. That's a waste of space.

Sometimes, you can find a cell that has a small diffusion relative to the cell height and they have a diffision "arm" to reach out the power/gnd rail and have a lot of unsed area between power/gnd rail and diffusion. That's not a good practice in terms of area utilization.

Connecting multiple cells in parallel doesn't have this issue.

Go look at the actual cell layout on GDS or other forms and see how the cell layout, especially the diffusion and poly, is designed and you'll know what I mean.