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A simple way is : using a delay line ( fabricated delay lines are available from different manufacturers) and use a fast logic circuit for AND the main pulse and delayed pulse.
if peak voltage is small not several ten volt
you can prepair odd number inverters and even number inverters
then take AND
if you use CMOS device for 130nm , the pulse width is around
the
single inverter propagation delay that is 50 pSEC without pad capacitor
nor LOAD capacitor
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