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What is the race condition and how to avoid it?

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deh_fuhrer

deh_fuhrer

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Hi friends,
I am new to digital design.Could anybody please tell me what is race condition.how to avoid it.What is metastability.And what is the concept of clock gating.
 

Re: A Query

A race condition is a result of poor design for a latch or flip-flop. It denotes a condition in which the data and clock are changing at the same time and the result depends on which one wins.

In rare cases the data can be exactly on the threshold between a 0 and 1 and when the clock changes, the output actually stays between a 0 and 1 for a while (for example in a 5V system the output may stay around 2.5 volts for a short time (microseconds, maybe). When this happens the output is said to be 'metastable'. This could have serious effects on the operation of the system and worse, could be virtually impossible to duplicate and thus very hard to find and fix.
This same problem can exist at inputs to a logic gate and produce unwanted 'glitches'.

In order to prevent these design flaws, the designer needs to do a 'worst case timing analysis' on all the logic. This analysis uses propagation delays, rise and fall times, threshold points, etc. to calculate timings. He must do both minimum and maximum times for each device and choose the worst case combinations. In a large system this can be very time consuming but there are tools to aid in this analysis.

Power gating is used to simply turn the clock on and off (or gate the clock) to sections of logic that aren't in use for periods of time. This results in a reduction in power.
 

    deh_fuhrer

    deh_fuhrer

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Re: A Query

I was asked in an interview about the ideal point in the waveform to perform clock gating.Could you specify it more clearly where the clock gating could be performed and where it is avoided.
 

Re: A Query

The ideal place to start (and stop) clock gating is in the middle of the part of the clock that is low. (Assuming your gate control goes low to inhibit the clock and you're using an AND gate).

The idea is that when you switch the gate on and off, you don't want to generate any extra state changes or glitches on the clock line, and you don't want to shorten the clock pulse. So the safest place to do this is when the clock is low and the middle part is the safest.
 

    deh_fuhrer

    deh_fuhrer

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Re: A Query

newelltech said:
A race condition is a result of poor design for a latch or flip-flop. It denotes a condition in which the data and clock are changing at the same time and the result depends on which one wins.

In rare cases the data can be exactly on the threshold between a 0 and 1 and when the clock changes, the output actually stays between a 0 and 1 for a while (for example in a 5V system the output may stay around 2.5 volts for a short time (microseconds, maybe). When this happens the output is said to be 'metastable'. This could have serious effects on the operation of the system and worse, could be virtually impossible to duplicate and thus very hard to find and fix.
This same problem can exist at inputs to a logic gate and produce unwanted 'glitches'.

In order to prevent these design flaws, the designer needs to do a 'worst case timing analysis' on all the logic. This analysis uses propagation delays, rise and fall times, threshold points, etc. to calculate timings. He must do both minimum and maximum times for each device and choose the worst case combinations. In a large system this can be very time consuming but there are tools to aid in this analysis.

Power gating is used to simply turn the clock on and off (or gate the clock) to sections of logic that aren't in use for periods of time. This results in a reduction in power.
Click to expand...


Does race condition also refer to the unwanted state which appears depending on changing sequence of logic state?
 

    deh_fuhrer

    deh_fuhrer

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Re: A Query

Sorry, I don't understand your question. If you're asking about metastable levels at an input being a race condition, I wouldn't call it a race condition.
Generally, once a race condition is discovered, the designer doesn't continue the analyis of that logic including any metastable states. The race condition must be fixed which will prevent the metastable state.
 

    deh_fuhrer

    deh_fuhrer

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A Query

is it related to master slave FF ??
 

    deh_fuhrer

    deh_fuhrer

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Re: A Query

It is a general problem related to most of the Flip-Flops.
 

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