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Check my VHDL code for actel FPGA

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M

mobile-it

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I am trying to learn the synthesize process for my actel FPGA

I get problem with the following code:

entity UART_CLK is
port (
clk : in std_ulogic;
rst : in std_ulogic;
CLK384 : out std_ulogic
);
end UART_CLK;
architecture behavioral of UART_CLK is
signal clkDiv : std_logic_vector(7 downto 0);
signal CLKt : std_ulogic;
constant baudDivide : std_logic_vector(7 downto 0) := X"82";
begin
process (clk, rst)
begin
if (rst = '1') then
clkDiv <= baudDivide;
CLKt <= '0';
elsif (clk = '1' and clk'event) then
if (clkDiv = X"00") then
clkDiv <= baudDivide;
CLKt <= not CLKt;
else
clkDiv <= clkDiv - 1;
end if;
end if;
end process;
CLK384 <= CLKt;
end behavioral;


What is wrong with this?

thank you for helping.
 

Re: VHDL Code problem

mobile-it said:
I am trying to learn the synthesize process for my actel FPGA

I get problem with the following code:

entity UART_CLK is
port (
clk : in std_ulogic;
rst : in std_ulogic;
CLK384 : out std_ulogic
);
end UART_CLK;
architecture behavioral of UART_CLK is
signal clkDiv : std_logic_vector(7 downto 0);
signal CLKt : std_ulogic;
constant baudDivide : std_logic_vector(7 downto 0) := X"82";
begin
process (clk, rst)
begin
if (rst = '1') then
clkDiv <= baudDivide;
CLKt <= '0';
elsif (clk = '1' and clk'event) then
if (clkDiv = X"00") then
clkDiv <= baudDivide;
CLKt <= not CLKt;
else
clkDiv <= clkDiv - 1;
end if;
end if;
end process;
CLK384 <= CLKt;
end behavioral;


What is wrong with this?

thank you for helping.
Click to expand...

Hi!
Put header :D

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;
 

    M

    mobile-it

    Points: 2
    Helpful Answer Positive Rating
VHDL Code problem

i am beginner in vhdl so may be some guru can correct if wrong . You are trying to perform math on std_logic_vector (sub operation). Actually it should be done if library std_logic_arith is included into source code. Bit i tested that on ahdl activehdl : fucntion "-"
op1 with std_logic_vector and op2 Integer is not visible from library .
then i rewrote your code and get it compiled as below :
Code: 
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.std_logic_arith.all;  -- this library should contain "-" functions for logic_vector's but statement did not work 

entity UART_CLK is
	port (
		clk : in std_ulogic;
		rst : in std_ulogic;
		CLK384 : out std_ulogic);
end UART_CLK;				   

architecture behavioral of UART_CLK is
	signal clkDiv : INTEGER RANGE 0 TO 255;
	signal CLKt : std_ulogic;
	constant baudDivide : INTEGER RANGE 0 TO 255 := 130;
begin
	process (clk, rst)
	begin
		if (rst = '1') then
			clkDiv <= baudDivide;
			CLKt <= '0';
		elsif (clk = '1' and clk'event) then
			if (clkDiv = 0) then
				clkDiv <= baudDivide;
				CLKt <= not CLKt;
			else
				clkDiv <= clkDiv - 1;
			end if;
		end if;
	end process;
	CLK384 <= CLKt;
end behavioral;
 

    M

    mobile-it

    Points: 2
    Helpful Answer Positive Rating
Re: VHDL Code problem

ModelSim simulates and compiles the next code correctly, it works:

Code: 
library IEEE;
use IEEE.std_logic_1164.all;      
--use IEEE.std_logic_arith.all;
use IEEE.std_logic_unsigned.all;

entity UART_CLK is 
port ( 
clk : in std_ulogic; 
rst : in std_ulogic; 
CLK384 : out std_ulogic 
); 
end UART_CLK; 
architecture behavioral of UART_CLK is 
signal clkDiv : std_logic_vector(7 downto 0); 
signal CLKt : std_ulogic; 
constant baudDivide : std_logic_vector(7 downto 0) := X"82"; 

begin 
process (clk, rst) 
begin 
if (rst = '1') then 
  clkDiv <= baudDivide; 
  CLKt <= '0'; 
elsif (clk = '1' and clk'event) then 
  if (clkDiv = X"00") then 
    clkDiv <= baudDivide; 
    CLKt <= not CLKt; 
  else 
    clkDiv <= clkDiv - 1; 
  end if; 
end if; 
end process; 

CLK384 <= CLKt; 
end behavioral;
 

    M

    mobile-it

    Points: 2
    Helpful Answer Positive Rating
Re: VHDL Code problem

OMG.

Thank you guys for helping me out.

I just tried to synthesize the circuit using the Synplicity Synthesis tool included in Libero and this works... I will check later today on my FPGA board.


Thank you very much!
 

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