semitao
Junior Member level 3
![Junior Member level 3](/styles/images/ranks/clevel3.gif)
Hi,all.
I want to design a PLL, but I don't know the PLL design flow. As I know, I should construct the phase-domain model in verilogA first. Then the time-domain model, and the circuit at last.
In the phase-domain simulation, I should do the AC simulation for the loop bandwidth and phase margin, then caculate the loop filter parameter. In the time-domain simulation, I should do the tran simulation for the lock time, and I can substitute the circuit block for the verilogA block, then iterate the process for a good result.
I don't know in which step I can simulate the noise performance. Which simulation should I do in phase-domain model, time-domain model and circuit? And in the design flow, which parameter in each step I should concern?
Best Regards!![Big grin :D :D](data:image/gif;base64,R0lGODlhAQABAIAAAAAAAP///yH5BAEAAAAALAAAAAABAAEAAAIBRAA7)
I want to design a PLL, but I don't know the PLL design flow. As I know, I should construct the phase-domain model in verilogA first. Then the time-domain model, and the circuit at last.
In the phase-domain simulation, I should do the AC simulation for the loop bandwidth and phase margin, then caculate the loop filter parameter. In the time-domain simulation, I should do the tran simulation for the lock time, and I can substitute the circuit block for the verilogA block, then iterate the process for a good result.
I don't know in which step I can simulate the noise performance. Which simulation should I do in phase-domain model, time-domain model and circuit? And in the design flow, which parameter in each step I should concern?
Best Regards!