What's the proper design flow for a PLL?

Hi,all.
I want to design a PLL, but I don't know the PLL design flow. As I know, I should construct the phase-domain model in verilogA first. Then the time-domain model, and the circuit at last.
In the phase-domain simulation, I should do the AC simulation for the loop bandwidth and phase margin, then caculate the loop filter parameter. In the time-domain simulation, I should do the tran simulation for the lock time, and I can substitute the circuit block for the verilogA block, then iterate the process for a good result.
I don't know in which step I can simulate the noise performance. Which simulation should I do in phase-domain model, time-domain model and circuit? And in the design flow, which parameter in each step I should concern?

Best Regards!

How to design a PLL?

The design depens on the applcation of te PLL.

I recomend you the book of PhD Rolan E. Best
you can find it in the upload/download section

Good luck

Re: How to design a PLL?

If my pll is a frequency synthesizer, how about the design flow?

Re: How to design a PLL?

Well, I'd reccomend that you start with the specifications that the PLL is intended to meet. Things such as lock time, Phase noise, spurious output, power consumption reference frequency etc.

Once you have those, you can do a simple linear analysis of the PLL with Matlab/MathCAD to determine things like the loop filter bandwidth, the VCO Phase Noise, the Allowable divider noise & Jitter, Dead Zone, etc. All of this can be done with a linear S-domain simulator.

once you have those, you can start looking at the blocks, because you will have enough information to design the VCO and dividers. Once you have a first pass at the specifications of the blocks, you can go back to the linear simulator to make sure that your spec's will be met.

How is that?

Dave
www.keystoneradio.com

Re: How to design a PLL?

Thanks, Dave
I haven't use the Matlab, I just construct a phase-domain model in verilogA. I can simulate it for bandwidth, but I don't know how to simulate the phase noise. Because I even don't know how to specify the detailed noise parameter in the verilogA block or simulator option.

How to design a PLL?

you design it by language?

How to design a PLL?

No, I just establish the phase-domain and time-domain model in VerilogA. I will design the circuit.

How to design a PLL?

hi!

i suggest you first fix the architecture. then you go for deriving the system level parameters of the PLL. verify these parameters using a behavioral langauge like verilog/vhdl/matlab. after you have the required performance of the PLL go for deriving the block level specifications using the system level parameters. use the specs to implement blocks using CMOS transistors. this was the flow i used for my project.

regards,
vijay

How to design a PLL?

thanks