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Verilog Code : 'define & parameter

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choonlle

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verilog parameter

What is the different between parameter and define ??



May u give some examples...


I feel diff to understand the diff between both of them.


Thanks!
 

verilog define

Parameter is a data type in verilog. It is used to declare constants which are not modified during runtime. Where as we can use defparam statement for updating the parameter.

'define is a macro that can be used to define any variable, function or exprassion under a name. U can use the macro for a given data in ur code with ' identifier

Added after 25 minutes:

Go through this its really useful for beginners

**broken link removed**
 
verilog define parameter

`define is a macro. You use it in the same way that you use macros in C language.

A parameter, on the other hand, will become a membor of your module. Imagin you write a code for a generic adder with a WIDTH parameter as the width of its input/output ports. Now, you can instantiate the same adder several times with a different value for the WIDTH parameter.

Example
module adder (a,b,c);
parameter WIDTH = 2; //defult value
input [WIDTH-1:0] a;
input [WIDTH-1:0] b;
output [WIDTH-1:0] c;

assign c=a+b;
endmodule

The instantiation will look like this:

adder #( 4 ) adder1 (a,b,c); // a four bit adder
adder #( 8 ) adder1 (a,b,c); // an eight bit adder

Now, think about it, could you do the above example, using macros?
 
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verilog `define

Hi
ourarash is correct
Parameters allows you to have configurable hardware at the compliation time.
defines manily are used as a complier directive (to be used with `ifdef and `ifndef)

Thanks
Haytham
 

define verilog

thanks a lot
 

`define verilog

but be careful about the scope. `define is universal...so anything gets compiled and use that `define will get the value.
 

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