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I normally do layout for MOS and never had drawn a BJT... How do you draw it? what must I check while drawing it?; regardless of DRC and LVS...
Thanks...
for bjt the emitter base and collector are the terminals that should be considered. take note that in bjt collector may always be connected to VSS or grouund
The BJT layout mainly depends on the technology you are using...its shape differs from one fab to the other and from one technology to the other. Also the BJT usually has two or three fixed shapes with diffrent sizes for each technology, and it is provided in the design kit you are using.
In doing the layout of BJT we usually place them frame to frame to save area for the chip. we also avoid passing wires on the three terminals especilly on emitter area.
We have a matching considerations also for bjt (common centroid). Ex. Q1 & Q2<0:7> needs to place common centroid. You can place them 3rows and 3columns w/c is equal to 9. The center 1 is Q1 & 8 pcs of Q2 is surrounding Q1. This is the manner of doing common centroid BJT.
my above example is not only for memory or ovonics technology, this common centroid can be use for any process or technology as long as we need to consider the matching of the 2 transistors. this is just an example of common centroid for bjt transistor to maintain the environment of the 2 transistors.
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